linux-kernel - Re: [PATCH] tools/memory-model: Provide extra ordering for unlock+lock pair on the same CPU

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Message-ID: <mhng-9504267b-2dee-4c16-b7a5-4c4360066b5e@palmerdabbelt-glaptop>
Date:   Fri, 08 Oct 2021 09:32:58 -0700 (PDT)
From:   Palmer Dabbelt <palmer@...belt.com>
To:     boqun.feng@...il.com
CC:     mpe@...erman.id.au, linux-kernel@...r.kernel.org,
        paulmck@...nel.org, Daniel Lustig <dlustig@...dia.com>,
        will@...nel.org, peterz@...radead.org,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        alexander.shishkin@...ux.intel.com, hpa@...or.com,
        parri.andrea@...il.com, mingo@...nel.org, vincent.weaver@...ne.edu,
        tglx@...utronix.de, jolsa@...hat.com, acme@...hat.com,
        eranian@...gle.com, Paul Walmsley <paul.walmsley@...ive.com>,
        stern@...land.harvard.edu, linux-arch@...r.kernel.org
Subject:     Re: [PATCH] tools/memory-model: Provide extra ordering for unlock+lock pair on the same CPU

On Thu, 07 Oct 2021 23:54:23 PDT (-0700), boqun.feng@...il.com wrote:
> On Fri, Oct 08, 2021 at 04:30:37PM +1100, Michael Ellerman wrote:
>> Boqun Feng <boqun.feng@...il.com> writes:
>> > (Add linux-arch in Cc list)
>> >
>> > Architecture maintainers, this patch is about strengthening our memory
>> > model a little bit, your inputs (confirmation, ack/nack, etc.) are
>> > appreciated.
>>
>> Hi Boqun,
>>
>> I don't feel like I'm really qualified to give an ack here, you and the
>> other memory model folk know this stuff much better than me.
>>
>> But I have reviewed it and it matches my understanding of how our
>> barriers work, so it looks OK to me.
>>
>> Reviewed-by: Michael Ellerman <mpe@...erman.id.au> (powerpc)

I'm basically in the same spot.  I think I said something to that effect 
somewhere in the thread, but I'm not sure if it got picked up so

Acked-by: Palmer Dabbelt <palmerdabbelt@...gle.com> (RISC-V)

(I don't feel comfortable reviewing it so I'm acking it, not sure if I'm 
just backwards about what all this means though ;)).

IIUC this change will mean the RISC-V port is broken, but I'm happy to 
fix it.  Were you guys trying to target this for 5.16?