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Date:   Sun, 10 Oct 2021 13:15:51 +0200
From:   Ansuel Smith <>
To:     Andrew Lunn <>,
        Vivien Didelot <>,
        Florian Fainelli <>,
        Vladimir Oltean <>,
        "David S. Miller" <>,
        Jakub Kicinski <>,
        Rob Herring <>,
        Russell King <>,,,
Cc:     Ansuel Smith <>
Subject: [net-next PATCH v4 08/13] dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll

Document qca,sgmii-enable-pll binding used in the CPU nodes to
enable SGMII PLL on MAC config.

Signed-off-by: Ansuel Smith <>
 Documentation/devicetree/bindings/net/dsa/qca8k.txt | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
index aeb206556f54..05a8ddfb5483 100644
--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt
+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
@@ -45,6 +45,16 @@ A CPU port node has the following optional node:
                                 Mostly used in qca8327 with CPU port 0 set to
 - qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge.
+- qca,sgmii-enable-pll  : For SGMII CPU port, explicitly enable PLL, TX and RX
+                          chain along with Signal Detection.
+                          This should NOT be enabled for qca8327. If enabled with
+                          qca8327 the sgmii port won't correctly init and an err
+                          is printed.
+                          This can be required for qca8337 switch with revision 2.
+                          A warning is displayed when used with revision greater
+                          2.
+                          With CPU port set to sgmii and qca8337 it is advised
+                          to set this unless a communication problem is observed.
 For QCA8K the 'fixed-link' sub-node supports only the following properties:

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