linux-kernel - [PATCH 5/5] clk: x86: Fix clk_gate_flags for RV_CLK

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20211011044528.66109-5-AjitKumar.Pandey@amd.com>
Date:   Mon, 11 Oct 2021 10:15:26 +0530
From:   Ajit Kumar Pandey <AjitKumar.Pandey@....com>
To:     <sboyd@...eaurora.org>, <linux-clk@...r.kernel.org>
CC:     <Vijendar.Mukunda@....com>, <Basavaraj.Hiregoudar@....com>,
        <Sunil-kumar.Dommati@....com>, <Alexander.Deucher@....com>,
        Ajit Kumar Pandey <AjitKumar.Pandey@....com>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        open list <linux-kernel@...r.kernel.org>
Subject: [PATCH 5/5] clk: x86: Fix clk_gate_flags for RV_CLK_GATE

In AMD's SoC we have to clear bit for disabling 48MHz oscillator
clock gate. Remove CLK_GATE_SET_TO_DISABLE flag for proper enable
and disable of 48MHz clock.

Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@....com>
---
 drivers/clk/x86/clk-fch.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/x86/clk-fch.c b/drivers/clk/x86/clk-fch.c
index 9fcf452e28d6..7279f592012e 100644
--- a/drivers/clk/x86/clk-fch.c
+++ b/drivers/clk/x86/clk-fch.c
@@ -66,7 +66,7 @@ static int fch_clk_probe(struct platform_device *pdev)
 
 		hws[CLK_GATE_FIXED] = clk_hw_register_gate(NULL, "oscout1",
 			"clk48MHz", 0, fch_data->base + MISCCLKCNTL1,
-			OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL);
+			OSCCLKENB, 0, NULL);
 
 		devm_clk_hw_register_clkdev(&pdev->dev, hws[CLK_GATE_FIXED],
 					    fch_data->name, NULL);
-- 
2.25.1