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Message-Id: <20211011160236.6815-1-dafna.hirschfeld@collabora.com>
Date:   Mon, 11 Oct 2021 18:02:36 +0200
From:   Dafna Hirschfeld <dafna.hirschfeld@...labora.com>
To:     linux-media@...r.kernel.org
Cc:     Dafna Hirschfeld <dafna.hirschfeld@...labora.com>,
        kernel@...labora.com, acourbot@...omium.org,
        andrew-ct.chen@...iatek.com, courbot@...omium.org,
        dafna3@...il.com, eizan@...omium.org, enric.balletbo@...labora.com,
        houlong.wei@...iatek.com, hsinyi@...omium.org, hverkuil@...all.nl,
        irui.wang@...iatek.com, maoguang.meng@...iatek.com,
        matthias.bgg@...il.com, mchehab@...nel.org,
        minghsiu.tsai@...iatek.com, tfiga@...omium.org,
        tiffany.lin@...iatek.com, Rob Herring <robh+dt@...nel.org>,
        linux-kernel@...r.kernel.org, linux-mediatek@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org (moderated list:ARM/Mediatek SoC
        support),
        devicetree@...r.kernel.org (open list:OPEN FIRMWARE AND FLATTENED
        DEVICE TREE BINDINGS)
Subject: [PATCH] arm64: dts: mediatek: mt8173: remove double 'assigned-clocks' binding

The clock '<&topckgen CLK_TOP_VENC_LT_SEL>' is declared twice
in an 'assigned-clocks' list - in vcodec_dec and in
vcodec_enc_vp8. Fix it to be declared only in vcodec_enc_vp8

Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@...labora.com>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index d9e005ae5bb0..51781444cedd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -1422,15 +1422,13 @@
 				      "vencpll",
 				      "venc_lt_sel",
 				      "vdec_bus_clk_src";
-			assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
-					  <&topckgen CLK_TOP_CCI400_SEL>,
+			assigned-clocks = <&topckgen CLK_TOP_CCI400_SEL>,
 					  <&topckgen CLK_TOP_VDEC_SEL>,
 					  <&apmixedsys CLK_APMIXED_VCODECPLL>,
 					  <&apmixedsys CLK_APMIXED_VENCPLL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
-						 <&topckgen CLK_TOP_UNIVPLL_D2>,
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D2>,
 						 <&topckgen CLK_TOP_VCODECPLL>;
-			assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
+			assigned-clock-rates = <0>, <0>, <1482000000>, <800000000>;
 		};
 
 		larb1: larb@...10000 {
-- 
2.17.1

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