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Date: Mon, 11 Oct 2021 03:30:17 +0200 From: Ansuel Smith <ansuelsmth@...il.com> To: Andrew Lunn <andrew@...n.ch>, Vivien Didelot <vivien.didelot@...il.com>, Florian Fainelli <f.fainelli@...il.com>, Vladimir Oltean <olteanv@...il.com>, "David S. Miller" <davem@...emloft.net>, Jakub Kicinski <kuba@...nel.org>, Rob Herring <robh+dt@...nel.org>, Russell King <linux@...linux.org.uk>, netdev@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org Cc: Ansuel Smith <ansuelsmth@...il.com> Subject: [net-next PATCH v5 07/14] dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll Document qca,sgmii-enable-pll binding used in the CPU nodes to enable SGMII PLL on MAC config. Signed-off-by: Ansuel Smith <ansuelsmth@...il.com> --- Documentation/devicetree/bindings/net/dsa/qca8k.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index aeb206556f54..05a8ddfb5483 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -45,6 +45,16 @@ A CPU port node has the following optional node: Mostly used in qca8327 with CPU port 0 set to sgmii. - qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge. +- qca,sgmii-enable-pll : For SGMII CPU port, explicitly enable PLL, TX and RX + chain along with Signal Detection. + This should NOT be enabled for qca8327. If enabled with + qca8327 the sgmii port won't correctly init and an err + is printed. + This can be required for qca8337 switch with revision 2. + A warning is displayed when used with revision greater + 2. + With CPU port set to sgmii and qca8337 it is advised + to set this unless a communication problem is observed. For QCA8K the 'fixed-link' sub-node supports only the following properties: -- 2.32.0
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