[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <fe8833a4-df21-475b-7ddf-dcda54550652@gmail.com>
Date: Sun, 10 Oct 2021 19:11:23 -0700
From: Florian Fainelli <f.fainelli@...il.com>
To: Ansuel Smith <ansuelsmth@...il.com>, Andrew Lunn <andrew@...n.ch>,
Vivien Didelot <vivien.didelot@...il.com>,
Vladimir Oltean <olteanv@...il.com>,
"David S. Miller" <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Russell King <linux@...linux.org.uk>, netdev@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [net-next PATCH v5 06/14] net: dsa: qca8k: rework rgmii delay
logic and scan for cpu port 6
On 10/10/2021 6:30 PM, Ansuel Smith wrote:
> Future proof commit. This switch have 2 CPU port
Plural: ports.
> and one valid
> configuration is first CPU port set to sgmii and second CPU port set to
> regmii-id.
rgmii-id
> The current implementation detects delay only for CPU port
> zero set to rgmii and doesn't count any delay set in a secondary CPU
> port. Drop the current delay scan function and move it to the sgmii
> parser function to generilize
generalize
> and implicitly add support for secondary
> CPU port set to rgmii-id. Introduce new logic where delay is enabled
> also with internal delay binding declared and rgmii set as PHY mode.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@...il.com>
Otherwise, looking good to me.
--
Florian
Powered by blists - more mailing lists