linux-kernel - linux-next: manual merge of the tip tree with Linus' tree

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Message-ID: <20211011132120.7bdb70d9@canb.auug.org.au>
Date:   Mon, 11 Oct 2021 13:21:20 +1100
From:   Stephen Rothwell <sfr@...b.auug.org.au>
To:     Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>,
        "H. Peter Anvin" <hpa@...or.com>,
        Peter Zijlstra <peterz@...radead.org>
Cc:     Borislav Petkov <bp@...e.de>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Linux Next Mailing List <linux-next@...r.kernel.org>
Subject: linux-next: manual merge of the tip tree with Linus' tree

Hi all,

Today's linux-next merge of the tip tree got a conflict in:

  arch/x86/kernel/fpu/signal.c

between commit:

  d298b03506d3 ("x86/fpu: Restore the masking out of reserved MXCSR bits")

from Linus' tree and commits:

  052adee66828 ("x86/fpu/signal: Change return type of copy_fpstate_to_sigframe() to boolean")
  908d969f88bf ("x86/fpu: Restore the masking out of reserved MXCSR bits")

from the tip tree.

I fixed it up (I just used the version form Linus' tree, but with the
changed return type - see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc arch/x86/kernel/fpu/signal.c
index fa17a27390ab,ae51e50f25e8..000000000000
--- a/arch/x86/kernel/fpu/signal.c
+++ b/arch/x86/kernel/fpu/signal.c
@@@ -377,16 -382,10 +382,16 @@@ static bool __fpu_restore_sig(void __us
  	} else {
  		if (__copy_from_user(&fpu->state.fxsave, buf_fx,
  				     sizeof(fpu->state.fxsave)))
- 			return -EFAULT;
+ 			return false;
  
 -		/* Mask out reserved MXCSR bits. */
 -		fpu->state.fxsave.mxcsr &= mxcsr_feature_mask;
 +		if (IS_ENABLED(CONFIG_X86_64)) {
 +			/* Reject invalid MXCSR values. */
 +			if (fpu->state.fxsave.mxcsr & ~mxcsr_feature_mask)
- 				return -EINVAL;
++				return false;
 +		} else {
 +			/* Mask invalid bits out for historical reasons (broken hardware). */
 +			fpu->state.fxsave.mxcsr &= ~mxcsr_feature_mask;
 +		}
  
  		/* Enforce XFEATURE_MASK_FPSSE when XSAVE is enabled */
  		if (use_xsave())

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