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Message-Id: <20211012183344.105637-1-wefu@redhat.com>
Date: Wed, 13 Oct 2021 02:33:42 +0800
From: wefu@...hat.com
To: anup.patel@....com, atish.patra@....com, palmerdabbelt@...gle.com,
guoren@...nel.org, christoph.muellner@...ll.eu,
philipp.tomsich@...ll.eu, hch@....de, liush@...winnertech.com,
wefu@...hat.com, lazyparser@...il.com, drew@...gleboard.org
Cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
taiten.peng@...onical.com, aniket.ponkshe@...onical.com,
heinrich.schuchardt@...onical.com, gordan.markus@...onical.com,
guoren@...ux.alibaba.com, arnd@...db.de, wens@...e.org,
maxime@...no.tech, dlustig@...dia.com, gfavor@...tanamicro.com,
andrea.mondelli@...wei.com, behrensj@....edu, xinhaoqu@...wei.com,
huffman@...ence.com, mick@....forth.gr,
allen.baum@...erantotech.com, jscheid@...tanamicro.com,
rtrauben@...il.com, Fu Wei <fu.wei@...aro.org>
Subject: [PATCH 0/2] riscv: Add RISC-V svpbmt extension supports
From: Fu Wei <fu.wei@...aro.org>
This patch follows the standard pure RISC-V Svpbmt extension in
privilege spec to solve the non-coherent SOC DMA synchronization
issues.
Wei Fu (2):
dt-bindings: riscv: Add mmu-supports with svpbmt
riscv: Add RISC-V svpbmt supports
.../devicetree/bindings/riscv/cpus.yaml | 5 +++
arch/riscv/include/asm/fixmap.h | 2 +-
arch/riscv/include/asm/pgtable-64.h | 8 ++--
arch/riscv/include/asm/pgtable-bits.h | 41 ++++++++++++++++++-
arch/riscv/include/asm/pgtable.h | 39 ++++++++++++++----
arch/riscv/kernel/cpufeature.c | 32 +++++++++++++++
arch/riscv/mm/init.c | 5 +++
7 files changed, 117 insertions(+), 15 deletions(-)
--
2.25.4
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