linux-kernel - Re: [PATCH v4 04/15] arm64: errata: Add detection for TRBE write to out-of-range

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Date:   Tue, 12 Oct 2021 08:35:25 -0700
From:   Randy Dunlap <rdunlap@...radead.org>
To:     Suzuki K Poulose <suzuki.poulose@....com>, will@...nel.org,
        mathieu.poirier@...aro.org
Cc:     catalin.marinas@....com, anshuman.khandual@....com,
        mike.leach@...aro.org, leo.yan@...aro.org, maz@...nel.org,
        coresight@...ts.linaro.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, Mark Rutland <mark.rutland@....com>
Subject: Re: [PATCH v4 04/15] arm64: errata: Add detection for TRBE write to
 out-of-range

On 10/12/21 6:17 AM, Suzuki K Poulose wrote:
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index b9b181470f0f..87a07e895db9 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -740,6 +740,47 @@ config ARM64_ERRATUM_2067961
>   
>   	  If unsure, say Y.
>   
> +config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
> +	bool
> +
> +config ARM64_ERRATUM_2253138
> +	bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
> +	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
> +	depends on CORESIGHT_TRBE
> +	default y
> +	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
> +	help
> +	  This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
> +
> +	  Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
> +	  for TRBE. Under some conditions, the TRBE might generate a write to the next
> +	  virtually addressed page following the last page of the TRBE address space
> +	  (i.e, the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.

	  (i.e.,

> +
> +	  We work around this in the driver by, always making sure that there is a

	  Work around this in the driver by always making sure that there is a

> +	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
> +
> +	  If unsure, say Y.
> +
> +config ARM64_ERRATUM_2224489
> +	bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range"
> +	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
> +	depends on CORESIGHT_TRBE
> +	default y
> +	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
> +	help
> +	  This option adds the workaround for ARM Cortex-A710 erratum 2224489.
> +
> +	  Affected Cortex-A710 cores might write to an out-of-range address, not reserved
> +	  for TRBE. Under some conditions, the TRBE might generate a write to the next
> +	  virtually addressed page following the last page of the TRBE address space
> +	  (i.e, the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.

	  (i.e.,

> +
> +	  We work around this in the driver by, always making sure that there is a

	  Work around this in the driver by always making sure that there is a

> +	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
> +
> +	  If unsure, say Y.


-- 
~Randy