linux-kernel - Re: [PATCH V3 1/2] dt-bindings: update riscv plic compatible string

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Message-ID: <CAJF2gTSJaYqH-=QQgM+d6jMQh1i97Q2=O9MCu_8jS2w06q5fCg@mail.gmail.com>
Date:   Wed, 13 Oct 2021 20:34:32 +0800
From:   Guo Ren <guoren@...nel.org>
To:     Heiko Stübner <heiko@...ech.de>
Cc:     Anup Patel <anup@...infault.org>,
        Atish Patra <atish.patra@....com>,
        Marc Zyngier <maz@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Palmer Dabbelt <palmer@...belt.com>,
        "linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        Guo Ren <guoren@...ux.alibaba.com>,
        Rob Herring <robh@...nel.org>,
        Palmer Dabbelt <palmerdabbelt@...gle.com>
Subject: Re: [PATCH V3 1/2] dt-bindings: update riscv plic compatible string

On Wed, Oct 13, 2021 at 4:57 PM Heiko Stübner <heiko@...ech.de> wrote:
>
> Hi Anup,
>
> Am Mittwoch, 13. Oktober 2021, 07:11:46 CEST schrieb Anup Patel:
> > On Wed, Oct 13, 2021 at 6:52 AM <guoren@...nel.org> wrote:
> > >
> > > From: Guo Ren <guoren@...ux.alibaba.com>
> > >
> > > Add the compatible string "thead,c900-plic" to the riscv plic
> > > bindings to support SOCs with thead,c9xx processor cores.
> > >
> > > Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
> > > Cc: Rob Herring <robh@...nel.org>
> > > Cc: Palmer Dabbelt <palmerdabbelt@...gle.com>
> > > Cc: Anup Patel <anup@...infault.org>
> > > Cc: Atish Patra <atish.patra@....com>
> > >
> > > ---
> > >
> > > Changes since V3:
> > >  - Rename "c9xx" to "c900"
> > >  - Add thead,c900-plic in the description section
> > > ---
> > >  .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml    | 6 ++++++
> > >  1 file changed, 6 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > > index 08d5a57ce00f..82629832e5a5 100644
> > > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > > @@ -35,6 +35,11 @@ description:
> > >    contains a specific memory layout, which is documented in chapter 8 of the
> > >    SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
> > >
> > > +  While the "thead,c900-plic" would mask IRQ with readl(claim), so it needn't
> > > +  mask/unmask which needed in RISC-V PLIC. When in IRQS_ONESHOT & IRQCHIP_EOI_THREADED
> > > +  path, unnecessary mask operation would cause a blocking irq bug in thead,c900-plic.
> > > +  Because when IRQ is disabled in c900, writel(hwirq, claim) would be invalid.
> >
> > This is a totally incorrect description of the errata required for C9xx PLIC.
> >
> > Please don't project non-compliance as a feature of C9xx PLIC.
> >
> > > +
> > >  maintainers:
> > >    - Sagar Kadam <sagar.kadam@...ive.com>
> > >    - Paul Walmsley  <paul.walmsley@...ive.com>
> > > @@ -46,6 +51,7 @@ properties:
> > >        - enum:
> > >            - sifive,fu540-c000-plic
> > >            - canaan,k210-plic
> > > +          - thead,c900-plic
>
> we still want specific SoC names in the compatible, the "c900"
> is still a sort-of placeholder.
c900 is not a SOC name, but a CPU name. For soc name, it should be
"allwinner,d1-plic".

>
>
> > >        - const: sifive,plic-1.0.0
> >
> > The PLIC DT node requires two compatible string:
> > <implementation_compat>, <spec_compat>
> >
> > The C9xx PLIC is not RISC-V PLIC so, the DT node should
> > be: "thead,c900-plic", "thead,c9xx-plic"
> >
> > You need to change "- const: sifive,plic-1.0.0" to
> > - enum:
> >     - sifive,plic-1.0.0
> >     - thead,c9xx-plic
>
>


-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/