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Message-ID: <8b509551-7cfa-f55c-fc0f-db7d0a3886eb@collabora.com>
Date: Thu, 14 Oct 2021 16:05:32 +0200
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: "jason-jh.lin" <jason-jh.lin@...iatek.com>,
Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Chun-Kuang Hu <chunkuang.hu@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>
Cc: Enric Balletbo i Serra <enric.balletbo@...labora.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
hsinyi@...omium.org, fshao@...omium.org, moudy.ho@...iatek.com,
roy-cw.yeh@...iatek.com, Fabien Parent <fparent@...libre.com>,
Yongqiang Niu <yongqiang.niu@...iatek.com>,
nancy.lin@...iatek.com, singo.chang@...iatek.com,
devicetree@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
dri-devel@...ts.freedesktop.org
Subject: Re: [PATCH v11 09/16] soc: mediatek: add mtk-mmsys support for mt8195
vdosys0
> Add mt8195 vdosys0 clock driver name and routing table to
> the driver data of mtk-mmsys.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@...iatek.com>
> ---
> This patch is base on [1]
> [1] soc: mediatek: mmsys: add mt8192 mmsys support
> - https://patchwork.kernel.org/project/linux-mediatek/list/?series=524857
>
> The vdosys1 impelmentation patch [2]
> [2] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
> - https://patchwork.kernel.org/project/linux-mediatek/patch/20210906071539.12953-7-nancy.lin@mediatek.com/
> ---
Hello Jason,
thanks for the patch! However, there are a few things to improve:
> drivers/soc/mediatek/mt8195-mmsys.h | 114 +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 11 +++
> include/linux/soc/mediatek/mtk-mmsys.h | 9 ++
> 3 files changed, 134 insertions(+)
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> new file mode 100644
> index 000000000000..0c97a5f016c1
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -0,0 +1,114 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> +
> +#define MT8195_VDO0_OVL_MOUT_EN 0xf14
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
> +
> +#define MT8195_VDO0_SEL_IN 0xf34
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
Bitshifting 0 by 0 bits == 0, so this is simply 0.
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
I would write 0x1 here
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
....and 0x2 here: bitshifting of 0 bits makes little sense.
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
Bitshifting 0 by 4 bits is still 0, so this is again 0.
This is repeated too many times, so I will not list it for all of the occurrences.
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
This is BIT(4).
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5) > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
...and this is BIT(5)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
BIT(8)
> +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
BIT(12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
BIT(13)
... and please, use the BIT(nr) macro for all these bit definitions, it's way more
readable like that.
Regards,
- Angelo
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