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Date:   Fri, 15 Oct 2021 20:30:28 +0200
From:   Lucas Stach <l.stach@...gutronix.de>
To:     Richard Zhu <hongxing.zhu@....com>, tharvey@...eworks.com,
        kishon@...com, vkoul@...nel.org, robh@...nel.org,
        galak@...nel.crashing.org, shawnguo@...nel.org
Cc:     linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        kernel@...gutronix.de, linux-imx@....com
Subject: Re: [PATCH v3 3/9] arm64: dts: imx8mm: add the pcie phy support

Am Dienstag, dem 12.10.2021 um 16:41 +0800 schrieb Richard Zhu:
> Add the PCIe PHY support on iMX8MM platforms.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index c2f3f118f82e..ac5d11466608 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1135,6 +1135,19 @@ usbmisc2: usbmisc@...50200 {
>  				reg = <0x32e50200 0x200>;
>  			};
>  
> +			pcie_phy: pcie-phy@...00000 {
> +				compatible = "fsl,imx8mm-pcie-phy";
> +				reg = <0x32f00000 0x10000>;
> +				clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
> +				clock-names = "phy";

Clock name specified in the binding is "ref".

> +				assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
> +				assigned-clock-rates = <100000000>;
> +				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
> +				resets = <&src IMX8MQ_RESET_PCIEPHY>;
> +				reset-names = "pciephy";
> +				#phy-cells = <0>;
> +				status = "disabled";
> +			};
>  		};
>  
>  		dma_apbh: dma-controller@...00000 {


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