linux-kernel - Re: [PATCH v6 04/16] dt-bindings: reset: mt8195: add vdosys1 reset control bit

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Message-ID: <CAAOTY_-9JdZfzF49E81Z046w=t0wDW7DScsVQQ2-L72mLXbjdg@mail.gmail.com>
Date:   Sat, 16 Oct 2021 07:41:52 +0800
From:   Chun-Kuang Hu <chunkuang.hu@...nel.org>
To:     "Nancy.Lin" <nancy.lin@...iatek.com>
Cc:     CK Hu <ck.hu@...iatek.com>,
        Chun-Kuang Hu <chunkuang.hu@...nel.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        David Airlie <airlied@...ux.ie>,
        Daniel Vetter <daniel@...ll.ch>,
        Rob Herring <robh+dt@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        "jason-jh . lin" <jason-jh.lin@...iatek.com>,
        Yongqiang Niu <yongqiang.niu@...iatek.com>,
        DRI Development <dri-devel@...ts.freedesktop.org>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@...ts.infradead.org>,
        DTML <devicetree@...r.kernel.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        singo.chang@...iatek.com,
        srv_heupstream <srv_heupstream@...iatek.com>
Subject: Re: [PATCH v6 04/16] dt-bindings: reset: mt8195: add vdosys1 reset
 control bit

Hi, Nancy:

Nancy.Lin <nancy.lin@...iatek.com> 於 2021年10月4日 週一 下午2:21寫道：
>
> Add vdosys1 reset control bit for MT8195 platform.

Reviewed-by: Chun-Kuang Hu <chunkuang.hu@...nel.org>

>
> Signed-off-by: Nancy.Lin <nancy.lin@...iatek.com>
> ---
>  include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
> index a26bccc8b957..aab8d74496a6 100644
> --- a/include/dt-bindings/reset/mt8195-resets.h
> +++ b/include/dt-bindings/reset/mt8195-resets.h
> @@ -26,4 +26,16 @@
>
>  #define MT8195_TOPRGU_SW_RST_NUM               16
>
> +/* VDOSYS1 */
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC          25
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC          26
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC          27
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC          28
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC          29
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC     51
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC     52
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC     53
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC     54
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC      55
> +
>  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
> --
> 2.18.0
>