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Date:   Fri, 15 Oct 2021 10:07:12 +0200
From:   Nicolas Ferre <nicolas.ferre@...rochip.com>
To:     Claudiu Beznea <claudiu.beznea@...rochip.com>,
        <mturquette@...libre.com>, <sboyd@...nel.org>,
        <alexandre.belloni@...tlin.com>, <ludovic.desroches@...rochip.com>
CC:     <linux-clk@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v5 13/15] clk: at91: sama7g5: remove prescaler part of
 master clock

On 11/10/2021 at 13:27, Claudiu Beznea wrote:
> On SAMA7G5 the prescaler part of master clock has been implemented as a
> changeable one. Everytime the prescaler is changed the PMC_SR.MCKRDY bit
> must be polled. Value 1 for PMC_SR.MCKRDY means the prescaler update is
> done. Driver polls for this bit until it becomes 1. On SAMA7G5 it has
> been discovered that in some conditions the PMC_SR.MCKRDY is not rising
> but the rate it provides it's stable. The workaround is to add a timeout
> when polling for PMC_SR.MCKRDY. At the moment, for SAMA7G5, the prescaler
> will be removed from Linux clock tree as all the frequencies for CPU could
> be obtained from PLL and also there will be less overhead when changing
> frequency via DVFS.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@...rochip.com>

Indeed:
Acked-by: Nicolas Ferre <nicolas.ferre@...rochip.com>

> ---
>   drivers/clk/at91/sama7g5.c | 11 +----------
>   1 file changed, 1 insertion(+), 10 deletions(-)
> 
> diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
> index c66bde6f7b47..fd9d17eabf54 100644
> --- a/drivers/clk/at91/sama7g5.c
> +++ b/drivers/clk/at91/sama7g5.c
> @@ -992,16 +992,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
>   	}
>   
>   	parent_names[0] = "cpupll_divpmcck";
> -	hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names,
> -					   &mck0_layout, &mck0_characteristics,
> -					   &pmc_mck0_lock,
> -					   CLK_SET_RATE_PARENT, 0);
> -	if (IS_ERR(hw))
> -		goto err_free;
> -
> -	sama7g5_pmc->chws[PMC_CPU] = hw;
> -
> -	hw = at91_clk_register_master_div(regmap, "mck0", "cpuck",
> +	hw = at91_clk_register_master_div(regmap, "mck0", "cpupll_divpmcck",
>   					  &mck0_layout, &mck0_characteristics,
>   					  &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5);
>   	if (IS_ERR(hw))
> 


-- 
Nicolas Ferre

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