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Date:   Fri, 15 Oct 2021 17:28:45 +0900
From:   Chanwoo Choi <>
To:     Samuel Holland <>,
        MyungJoo Ham <>,
        Kyungmin Park <>,
        Maxime Ripard <>,
        Chen-Yu Tsai <>,
        Jernej Skrabec <>,
        Rob Herring <>
Cc:     Michael Turquette <>,
        Stephen Boyd <>,,,,,
Subject: Re: [PATCH v2 6/6] PM / devfreq: Add a driver for the sun8i/sun50i

Hi Samuel,

On 10/4/21 10:27 AM, Samuel Holland wrote:
> This driver works by adjusting the divider on the DRAM controller's
> module clock. Thus there is no fixed set of OPPs, only "full speed" down
> to "quarter speed" (or whatever the maximum divider is on that variant).
> It makes use of the MDFS hardware in the MBUS, in "DFS" mode, which
> takes care of updating registers during the critical section while DRAM
> is inaccessible.
> This driver should support several sunxi SoCs, starting with the A33,
> which have a DesignWare DDR3 controller with merged PHY register space
> and the matching MBUS register layout (so not A63 or later). However,
> the driver has only been tested on the A64/H5, so those are the only
> compatibles enabled for now.
> Signed-off-by: Samuel Holland <>
> ---
>  drivers/devfreq/Kconfig          |   8 +
>  drivers/devfreq/Makefile         |   1 +
>  drivers/devfreq/sun8i-a33-mbus.c | 511 +++++++++++++++++++++++++++++++
>  3 files changed, 520 insertions(+)
>  create mode 100644 drivers/devfreq/sun8i-a33-mbus.c


Looks good to me.

Acked-by: Chanwoo Choi <>

Best Regards,
Chanwoo Choi
Samsung Electronics

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