linux-kernel - Re: [PATCH v8 15/15] KVM: x86/cpuid: Advise Arch LBR feature in CPUID

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Message-ID: <YWmVA3FQoGcprtlp@google.com>
Date:   Fri, 15 Oct 2021 14:49:39 +0000
From:   Sean Christopherson <seanjc@...gle.com>
To:     Like Xu <like.xu.linux@...il.com>
Cc:     Yang Weijiang <weijiang.yang@...el.com>, pbonzini@...hat.com,
        jmattson@...gle.com, vkuznets@...hat.com, wei.w.wang@...el.com,
        kvm@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v8 15/15] KVM: x86/cpuid: Advise Arch LBR feature in CPUID

On Fri, Oct 15, 2021, Like Xu wrote:
> On 15/10/2021 9:28 am, Yang Weijiang wrote:
> > On Fri, Oct 15, 2021 at 12:01:22AM +0000, Sean Christopherson wrote:
> > > s/Advise/Advertise
> > > 
> > > On Tue, Aug 24, 2021, Yang Weijiang wrote:
> > > > Add Arch LBR feature bit in CPU cap-mask to expose the feature.
> > > > Only max LBR depth is supported for guest, and it's consistent
> > > > with host Arch LBR settings.
> > > > 
> > > > Co-developed-by: Like Xu <like.xu@...ux.intel.com>
> > > > Signed-off-by: Like Xu <like.xu@...ux.intel.com>
> > > > Signed-off-by: Yang Weijiang <weijiang.yang@...el.com>
> > > > ---
> > > >   arch/x86/kvm/cpuid.c | 33 ++++++++++++++++++++++++++++++++-
> > > >   1 file changed, 32 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> > > > index 03025eea1524..d98ebefd5d72 100644
> > > > --- a/arch/x86/kvm/cpuid.c
> > > > +++ b/arch/x86/kvm/cpuid.c
> > > > @@ -88,6 +88,16 @@ static int kvm_check_cpuid(struct kvm_cpuid_entry2 *entries, int nent)
> > > >   		if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0)
> > > >   			return -EINVAL;
> > > >   	}
> > > > +	best = cpuid_entry2_find(entries, nent, 0x1c, 0);
> > > > +	if (best) {
> > > > +		unsigned int eax, ebx, ecx, edx;
> > > > +
> > > > +		/* Reject user-space CPUID if depth is different from host's.*/
> > > 
> > > Why disallow this?  I don't see why it would be illegal for userspace to specify
> > > fewer LBRs,
> 
> The emulation of guest LBR *depends* on the host LBR driver to save/restore
> LBRs entries (which are pass-through to the guest and store the guest branch
> instructions rips actually).
> 
> Currently, the host side does not support the use of different lbr depths on
> the same host to customize this part of the overhead. The host perf LBR
> driver assumes that the lbr depths of different tasks on different cpu's are
> the same and are the maximum value.

Yes, I assumed as much, but saving/restoring MSRs that the guest does not have
access to is not a functional issue, just a waste of cycles.