linux-kernel - Re: [PATCH V4 2/3] dt-bindings: update riscv plic compatible string

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Message-ID: <CAJF2gTQKc1DGcCy_sFjSs8p+VMNGHFrjO2uLZrHnjdD1pZ2RZg@mail.gmail.com>
Date:   Sat, 16 Oct 2021 20:56:51 +0800
From:   Guo Ren <guoren@...nel.org>
To:     Heiko Stuebner <heiko@...ech.de>
Cc:     Anup Patel <anup@...infault.org>,
        Atish Patra <atish.patra@....com>,
        Marc Zyngier <maz@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Palmer Dabbelt <palmer@...belt.com>,
        Rob Herring <robh@...nel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        Guo Ren <guoren@...ux.alibaba.com>,
        Palmer Dabbelt <palmerdabbelt@...gle.com>
Subject: Re: [PATCH V4 2/3] dt-bindings: update riscv plic compatible string

On Sat, Oct 16, 2021 at 6:35 PM Heiko Stuebner <heiko@...ech.de> wrote:
>
> Hi Guo,
>
> Am Samstag, 16. Oktober 2021, 05:21:59 CEST schrieb guoren@...nel.org:
> > From: Guo Ren <guoren@...ux.alibaba.com>
> >
> > Add the compatible string "thead,c900-plic" to the riscv plic
> > bindings to support allwinner d1 SOC which contains c906 core.
>
> The compatible strings sound good now, but some things below
>
> >
> > Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
> > Cc: Rob Herring <robh@...nel.org>
> > Cc: Palmer Dabbelt <palmerdabbelt@...gle.com>
> > Cc: Anup Patel <anup@...infault.org>
> > Cc: Atish Patra <atish.patra@....com>
> >
> > ---
> >
> > Changes since V4:
> >  - Update description in errata style
> >  - Update enum suggested by Anup, Heiko, Samuel
> >
> > Changes since V3:
> >  - Rename "c9xx" to "c900"
> >  - Add thead,c900-plic in the description section
> > ---
> >  .../interrupt-controller/sifive,plic-1.0.0.yaml       | 11 ++++++++++-
> >  1 file changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > index 08d5a57ce00f..272f29540135 100644
> > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > @@ -35,6 +35,12 @@ description:
> >    contains a specific memory layout, which is documented in chapter 8 of the
> >    SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
> >
> > +  The C9xx PLIC does not comply with the interrupt claim/completion process defined
> > +  by the RISC-V PLIC specification because C9xx PLIC will mask an IRQ when it is
> > +  claimed by PLIC driver (i.e. readl(claim) and the IRQ will be unmasked upon
> > +  completion by PLIC driver (i.e. writel(claim). This behaviour breaks the handling
> > +  of IRQS_ONESHOT by the generic handle_fasteoi_irq() used in the PLIC driver.
> > +
> >  maintainers:
> >    - Sagar Kadam <sagar.kadam@...ive.com>
> >    - Paul Walmsley  <paul.walmsley@...ive.com>
> > @@ -46,7 +52,10 @@ properties:
> >        - enum:
> >            - sifive,fu540-c000-plic
> >            - canaan,k210-plic
> > -      - const: sifive,plic-1.0.0
> > +      - enmu:
>
>         ^ spelling enum
>
> > +          - sifive,plic-1.0.0
> > +          - thead,c900-plic
> > +          - allwinner,sun20i-d1-plic
>
> but in general I'd think that you want something like
>
>   compatible:
>     oneOf:
>       - items:
>           - enum:
>               - sifive,fu540-c000-plic
>               - canaan,k210-plic
>           - const: sifive,plic-1.0.0
>       - items:
>           - enum:
>               - allwinner,sun20i-d1-plic
>           - const: thead,c900-plic
>
> Having only one item list would allow as valid combinations like
> "sifive,fu540-c000-plic", "thead,c900-plic" when checking the schema.
>
> With the oneOf and separate lists we can make sure that such
> "illegal" combinations get flagged by the dtbs_check
>
> [the enum with the single allwinner entry already leaves
>  room for later addition to the c900-plic variant]
Thx, I'll fix it in the next version.

another question: Is the allwinner_sun20i_d1_plic needed to IRQCHIP_DECLARE?

+IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", thead_c900_plic_init);
+IRQCHIP_DECLARE(allwinner_sun20i_d1_plic, "allwinner,sun20i-d1-plic",
thead_c900_plic_init);

>
> Heiko

>
>
>


--
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/