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Date: Sat, 16 Oct 2021 11:21:57 +0800 From: guoren@...nel.org To: guoren@...nel.org, anup@...infault.org, atish.patra@....com, maz@...nel.org, tglx@...utronix.de, palmer@...belt.com, heiko@...ech.de, robh@...nel.org Cc: linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org, Guo Ren <guoren@...ux.alibaba.com> Subject: [PATCH V4 0/3] irqchip: riscv: Add thead,c900-plic support From: Guo Ren <guoren@...ux.alibaba.com> Add the compatible string "thead,c900-plic" to the riscv plic bindings to support allwinner d1 SOC which contains c906 core. Changes since V4: - Update description in errata style - Update enum suggested by Anup, Heiko, Samuel - Update comment by Anup - Add cover-letter Changes since V3: - Rename "c9xx" to "c900" - Add thead,c900-plic in the description section - Add sifive_plic_chip and thead_plic_chip for difference Changes since V2: - Add a separate compatible string "thead,c9xx-plic" - set irq_mask/unmask of "plic_chip" to NULL and point irq_enable/disable of "plic_chip" to plic_irq_mask/unmask - Add a detailed comment block in plic_init() about the differences in Claim/Completion process of RISC-V PLIC and C9xx PLIC. Guo Ren (3): irqchip/sifive-plic: Add thead,c900-plic support dt-bindings: update riscv plic compatible string dt-bindings: vendor-prefixes: add T-Head Semiconductor .../sifive,plic-1.0.0.yaml | 11 +++++- .../devicetree/bindings/vendor-prefixes.yaml | 2 ++ drivers/irqchip/irq-sifive-plic.c | 34 +++++++++++++++++-- 3 files changed, 44 insertions(+), 3 deletions(-) -- 2.25.1
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