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Message-ID: <YW3PqhQHauDYRlwN@robh.at.kernel.org>
Date: Mon, 18 Oct 2021 14:48:58 -0500
From: Rob Herring <robh@...nel.org>
To: Bjorn Andersson <bjorn.andersson@...aro.org>
Cc: Kishon Vijay Abraham I <kishon@...com>,
Vinod Koul <vkoul@...nel.org>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
abhinavk@...eaurora.org, Stephen Boyd <sboyd@...nel.org>
Subject: Re: [PATCH v3 1/2] dt-bindings: phy: Introduce Qualcomm eDP/DP PHY
binding
On Sat, Oct 16, 2021 at 04:21:27PM -0700, Bjorn Andersson wrote:
> Introduce a binding for the eDP/DP PHY hardware block found in several
> different Qualcomm platforms.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@...aro.org>
> ---
>
> Changes since v2:
> - None
>
> .../devicetree/bindings/phy/qcom,edp-phy.yaml | 69 +++++++++++++++++++
> 1 file changed, 69 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> new file mode 100644
> index 000000000000..c258e4f7e332
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> @@ -0,0 +1,69 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/phy/qcom,edp-phy.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Qualcomm DP/eDP PHY
> +
> +maintainers:
> + - Bjorn Andersson <bjorn.andersson@...aro.org>
> +
> +description:
> + The Qualcomm DP/eDP PHY is found in a number of Qualcomm platform and
> + provides the physical interface for DisplayPort and Embedded Display Port.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,sc8180x-dp-phy
> + - qcom,sc8180x-edp-phy
Is there a difference between DP and eDP?
Perhaps note what that is if so.
> +
> + reg:
> + items:
> + - description: PHY base register block
> + - description: tx0 register block
> + - description: tx1 register block
> + - description: PLL register block
> +
> + clocks:
> + maxItems: 2
> +
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> +
> + "#clock-cells":
> + const: 1
> +
> + "#phy-cells":
> + const: 0
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - "#clock-cells"
> + - "#phy-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + phy@...2a00 {
> + compatible = "qcom,sc8180x-edp-phy";
> + reg = <0x0aec2a00 0x1c0>,
> + <0x0aec2200 0xa0>,
> + <0x0aec2600 0xa0>,
> + <0x0aec2000 0x19c>;
> +
> + clocks = <&dispcc 0>, <&dispcc 1>;
> + clock-names = "aux", "cfg_ahb";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> + };
> +...
> --
> 2.29.2
>
>
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