linux-kernel - Re: [regression] commit d298b03506d3 ("x86/fpu: Restore the masking out of reserved MXCSR bits")

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Message-ID: <YW0af/LXlfi36HZt@intel.com>
Date:   Mon, 18 Oct 2021 09:55:59 +0300
From:   Ville Syrjälä <ville.syrjala@...ux.intel.com>
To:     Borislav Petkov <bp@...en8.de>
Cc:     Ser Olmy <ser.olmy@...tonmail.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>,
        "H. Peter Anvin" <hpa@...or.com>, x86@...nel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [regression] commit d298b03506d3 ("x86/fpu: Restore the masking
 out of reserved MXCSR bits")

On Fri, Oct 15, 2021 at 01:04:28PM +0200, Borislav Petkov wrote:
> Ok, here it is.

Thanks. I got distracted by other shiny objects anyway, so
wouldn't even have gotten to cooking up a proper patch until
now.

> 
> Ser, I'd appreciate you running it too, to make sure your box is still
> ok.
> 
> Thx.
> 
> ---
> From: Borislav Petkov <bp@...e.de>
> Date: Fri, 15 Oct 2021 12:46:25 +0200
> Subject: [PATCH] x86/fpu: Mask out the invalid MXCSR bits properly
> MIME-Version: 1.0
> Content-Type: text/plain; charset=UTF-8
> Content-Transfer-Encoding: 8bit
> 
> This is a fix for the fix (yeah, /facepalm).
> 
> The correct mask to use is not the negation of the MXCSR_MASK but the
> actual mask which contains the supported bits in the MXCSR register.
> 
> Reported and debugged by Ville Syrjälä <ville.syrjala@...ux.intel.com>
> 
> Fixes: d298b03506d3 ("x86/fpu: Restore the masking out of reserved MXCSR bits")
> Signed-off-by: Borislav Petkov <bp@...e.de>
> Cc: <stable@...r.kernel.org>
> Link: https://lore.kernel.org/r/YWgYIYXLriayyezv@intel.com
> ---
>  arch/x86/kernel/fpu/signal.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c
> index fa17a27390ab..831b25c5e705 100644
> --- a/arch/x86/kernel/fpu/signal.c
> +++ b/arch/x86/kernel/fpu/signal.c
> @@ -385,7 +385,7 @@ static int __fpu_restore_sig(void __user *buf, void __user *buf_fx,
>  				return -EINVAL;
>  		} else {
>  			/* Mask invalid bits out for historical reasons (broken hardware). */
> -			fpu->state.fxsave.mxcsr &= ~mxcsr_feature_mask;
> +			fpu->state.fxsave.mxcsr &= mxcsr_feature_mask;
>  		}
>  
>  		/* Enforce XFEATURE_MASK_FPSSE when XSAVE is enabled */
> -- 
> 2.29.2
> 
> -- 
> Regards/Gruss,
>     Boris.
> 
> https://people.kernel.org/tglx/notes-about-netiquette

-- 
Ville Syrjälä
Intel