lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Mon, 18 Oct 2021 10:37:10 +0900 From: Kunihiko Hayashi <hayashi.kunihiko@...ionext.com> To: Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...com>, Rob Herring <robh+dt@...nel.org>, Masami Hiramatsu <mhiramat@...nel.org> Cc: linux-phy@...ts.infradead.org, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, Kunihiko Hayashi <hayashi.kunihiko@...ionext.com> Subject: [PATCH 5/8] phy: uniphier-pcie: Set VCOPLL clamp mode in PHY register Set VCOPLL clamp mode to mode 0 to avoid hardware unstable issue. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@...ionext.com> --- drivers/phy/socionext/phy-uniphier-pcie.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c index fde8aac5f4b6..2bd8df619712 100644 --- a/drivers/phy/socionext/phy-uniphier-pcie.c +++ b/drivers/phy/socionext/phy-uniphier-pcie.c @@ -51,6 +51,9 @@ #define PCL_PHY_R26 26 #define VCO_CTRL GENMASK(7, 4) /* Tx VCO adjustment value */ #define VCO_CTRL_INIT_VAL 5 +#define PCL_PHY_R28 28 +#define VCOPLL_CLMP GENMASK(3, 2) /* Tx VCOPLL clamp mode */ +#define VCOPLL_CLMP_VAL 0 struct uniphier_pciephy_priv { void __iomem *base; @@ -158,6 +161,8 @@ static int uniphier_pciephy_init(struct phy *phy) FIELD_PREP(RX_EQ_ADJ, RX_EQ_ADJ_VAL)); uniphier_pciephy_set_param(priv, PCL_PHY_R26, VCO_CTRL, FIELD_PREP(VCO_CTRL, VCO_CTRL_INIT_VAL)); + uniphier_pciephy_set_param(priv, PCL_PHY_R28, VCOPLL_CLMP, + FIELD_PREP(VCOPLL_CLMP, VCOPLL_CLMP_VAL)); usleep_range(1, 10); uniphier_pciephy_deassert(priv); -- 2.7.4
Powered by blists - more mailing lists