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Message-ID: <20211018114739.14026-4-sam.shih@mediatek.com>
Date: Mon, 18 Oct 2021 19:47:38 +0800
From: Sam Shih <sam.shih@...iatek.com>
To: Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Sean Wang <sean.wang@...nel.org>, <linux-gpio@...r.kernel.org>,
<devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>
CC: John Crispin <john@...ozen.org>,
Ryder Lee <Ryder.Lee@...iatek.com>,
"Sam Shih" <sam.shih@...iatek.com>
Subject: [PATCH v8 3/4] arm64: dts: mediatek: add pinctrl support for mt7986a
Add mt7986a pinctrl node, and update pinmux setting for mt7986a
Signed-off-by: Sam Shih <sam.shih@...iatek.com>
---
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 20 +++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 21 ++++++++++++++++++++
2 files changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
index ca074cf8e578..92e3f59c6cee 100644
--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
@@ -30,9 +30,29 @@ &uart0 {
};
&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
status = "okay";
};
+
+&pio {
+ uart1_pins: uart1-pins {
+ mux {
+ function = "uart";
+ groups = "uart1";
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ mux {
+ function = "uart";
+ groups = "uart2";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
index a8cf0eb79688..c59a27aa86e2 100644
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -128,6 +128,27 @@ apmixedsys: apmixedsys@...1e000 {
#clock-cells = <1>;
};
+ pio: pinctrl@...1f000 {
+ compatible = "mediatek,mt7986a-pinctrl";
+ reg = <0 0x1001f000 0 0x1000>,
+ <0 0x11c30000 0 0x1000>,
+ <0 0x11c40000 0 0x1000>,
+ <0 0x11e20000 0 0x1000>,
+ <0 0x11e30000 0 0x1000>,
+ <0 0x11f00000 0 0x1000>,
+ <0 0x11f10000 0 0x1000>,
+ <0 0x1000b000 0 0x1000>;
+ reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
+ "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 100>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ };
+
sgmiisys0: syscon@...60000 {
compatible = "mediatek,mt7986-sgmiisys_0",
"syscon";
--
2.29.2
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