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Message-ID: <CAL_Jsq+NM=jvYfvyNVsJCrizHzqaDMPe05hkBhnOWHc+JwBNig@mail.gmail.com>
Date:   Mon, 18 Oct 2021 07:02:15 -0500
From:   Rob Herring <robh@...nel.org>
To:     Guo Ren <guoren@...nel.org>
Cc:     Anup Patel <anup@...infault.org>,
        Atish Patra <atish.patra@....com>,
        Marc Zyngier <maz@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Palmer Dabbelt <palmer@...belt.com>,
        "heiko@...ech.de" <heiko@...ech.de>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        Guo Ren <guoren@...ux.alibaba.com>,
        Palmer Dabbelt <palmerdabbelt@...gle.com>
Subject: Re: [PATCH V4 2/3] dt-bindings: update riscv plic compatible string

On Fri, Oct 15, 2021 at 10:22 PM <guoren@...nel.org> wrote:
>
> From: Guo Ren <guoren@...ux.alibaba.com>
>
> Add the compatible string "thead,c900-plic" to the riscv plic
> bindings to support allwinner d1 SOC which contains c906 core.
>
> Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
> Cc: Rob Herring <robh@...nel.org>
> Cc: Palmer Dabbelt <palmerdabbelt@...gle.com>
> Cc: Anup Patel <anup@...infault.org>
> Cc: Atish Patra <atish.patra@....com>

Please send to the DT list so that checks run and it's in my review
queue (IOW, use get_maintainers.pl). And run 'make dt_binding_check'
so reviewers don't have to find your typos and other errors for you.

Rob

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