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Date:   Tue, 19 Oct 2021 18:59:51 +0200
From:   Paolo Bonzini <pbonzini@...hat.com>
To:     Wanpeng Li <kernellwp@...il.com>, linux-kernel@...r.kernel.org,
        kvm@...r.kernel.org
Cc:     Sean Christopherson <seanjc@...gle.com>,
        Vitaly Kuznetsov <vkuznets@...hat.com>,
        Wanpeng Li <wanpengli@...cent.com>,
        Jim Mattson <jmattson@...gle.com>,
        Joerg Roedel <joro@...tes.org>
Subject: Re: [PATCH v3 2/3] KVM: vPMU: Fill get_msr
 MSR_CORE_PERF_GLOBAL_OVF_CTRL w/ 0

On 19/10/21 10:12, Wanpeng Li wrote:
> From: Wanpeng Li <wanpengli@...cent.com>
> 
> SDM section 18.2.3 mentioned that:
> 
>    "IA32_PERF_GLOBAL_OVF_CTL MSR allows software to clear overflow indicator(s) of
>     any general-purpose or fixed-function counters via a single WRMSR."
> 
> It is R/W mentioned by SDM, we read this msr on bare-metal during perf testing,
> the value is always 0 for ICX/SKX boxes on hands. Let's fill get_msr
> MSR_CORE_PERF_GLOBAL_OVF_CTRL w/ 0 as hardware behavior and drop
> global_ovf_ctrl variable.
> 
> Tested-by: Like Xu <likexu@...cent.com>
> Signed-off-by: Wanpeng Li <wanpengli@...cent.com>
> ---
> Btw, xen also fills get_msr MSR_CORE_PERF_GLOBAL_OVF_CTRL w/ 0.
> v1 -> v2:
>   * drop 'u64 global_ovf_ctrl' directly
> 
>   arch/x86/include/asm/kvm_host.h | 1 -
>   arch/x86/kvm/vmx/pmu_intel.c    | 6 ++----
>   2 files changed, 2 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
> index f8f48a7ec577..7aaac918e992 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -499,7 +499,6 @@ struct kvm_pmu {
>   	u64 fixed_ctr_ctrl;
>   	u64 global_ctrl;
>   	u64 global_status;
> -	u64 global_ovf_ctrl;
>   	u64 counter_bitmask[2];
>   	u64 global_ctrl_mask;
>   	u64 global_ovf_ctrl_mask;
> diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
> index 10cc4f65c4ef..b8e0d21b7c8a 100644
> --- a/arch/x86/kvm/vmx/pmu_intel.c
> +++ b/arch/x86/kvm/vmx/pmu_intel.c
> @@ -365,7 +365,7 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>   		msr_info->data = pmu->global_ctrl;
>   		return 0;
>   	case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
> -		msr_info->data = pmu->global_ovf_ctrl;
> +		msr_info->data = 0;
>   		return 0;
>   	default:
>   		if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||
> @@ -423,7 +423,6 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>   		if (!(data & pmu->global_ovf_ctrl_mask)) {
>   			if (!msr_info->host_initiated)
>   				pmu->global_status &= ~data;
> -			pmu->global_ovf_ctrl = data;
>   			return 0;
>   		}
>   		break;
> @@ -588,8 +587,7 @@ static void intel_pmu_reset(struct kvm_vcpu *vcpu)
>   		pmc->counter = 0;
>   	}
>   
> -	pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status =
> -		pmu->global_ovf_ctrl = 0;
> +	pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status = 0;
>   
>   	intel_pmu_release_guest_lbr_event(vcpu);
>   }
> 

Queued, thanks.

Paolo

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