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Message-ID: <20211019233641.140275-1-Smita.KoralahalliChannabasappa@amd.com>
Date:   Tue, 19 Oct 2021 18:36:36 -0500
From:   Smita Koralahalli <Smita.KoralahalliChannabasappa@....com>
To:     <x86@...nel.org>, <linux-edac@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
CC:     Tony Luck <tony.luck@...el.com>, "H . Peter Anvin" <hpa@...or.com>,
        <yazen.ghannam@....com>, <Smita.KoralahalliChannabasappa@....com>
Subject: [PATCH v2 0/5] x86/mce: Handle error injection failures in mce-inject module

This series of patches handles the scenarios where error injection
fails silently on mce-inject module. It also cleans up the code by
replacing MCx_{STATUS, ADDR, MISC} macros with mca_msr_reg() and finally
returns error code to userspace on failures injecting the module.

Error injection fails if the bank is unpopulated (MCA_IPID register reads
zero) or if the platform enforces write ignored behavior on status
registers.

The first patch checks for an unpopulated bank by reading the value out
from MCA_IPID register and the fourth patch checks for writes ignored from
MCA_STATUS and MCA_DESTAT.

The second patch warns the user about MCA handlers missing signatures if
valid bit is not set in MCA_STATUS register before doing error injection.

The third patch does some cleanup by replacing MCx_{STATUS, ADDR, MISC}
macros with mca_msr_reg().

The final patch returns error code to userspace from mce-inject module.

Smita Koralahalli (5):
  x86/mce/inject: Check if a bank is unpopulated before error injection
  x86/mce/inject: Warn the user on a not set valid bit in MCA_STATUS
  x86/mce: Use mca_msr_reg() in prepare_msrs()
  x86/mce/inject: Check for writes ignored in status registers
  x86/mce/mce-inject: Return error code to userspace from mce-inject
    module

 arch/x86/kernel/cpu/mce/core.c   |   1 +
 arch/x86/kernel/cpu/mce/inject.c | 103 ++++++++++++++++++++++++-------
 2 files changed, 82 insertions(+), 22 deletions(-)

-- 
2.17.1

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