linux-kernel - Re: [PATCH v6 5/6] dt-bindings: mfd: Add Delta TN48M CPLD drivers bindings

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CA+HBbNH+4US9U_ZfGZHS2J-pBou2k1LCOAZwuestQHK1GmH0Eg@mail.gmail.com>
Date:   Tue, 19 Oct 2021 12:49:05 +0200
From:   Robert Marko <robert.marko@...tura.hr>
To:     Andrew Lunn <andrew@...n.ch>
Cc:     Linus Walleij <linus.walleij@...aro.org>,
        Rob Herring <robh@...nel.org>,
        Bartosz Golaszewski <bgolaszewski@...libre.com>,
        Lee Jones <lee.jones@...aro.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        devicetree <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Luka Perkov <luka.perkov@...tura.hr>,
        "Jonathan M. Polom" <jmp@...phyte.org>,
        Paul Menzel <pmenzel@...gen.mpg.de>,
        Donald Buczek <buczek@...gen.mpg.de>
Subject: Re: [PATCH v6 5/6] dt-bindings: mfd: Add Delta TN48M CPLD drivers bindings

On Tue, Oct 19, 2021 at 3:40 AM Andrew Lunn <andrew@...n.ch> wrote:
>
> > The SFP driver requires GPIO-s, it only knows how to use GPIO-s, and
> > its a generic driver,
> > it covers any device that has an SFP port that is implemented per spec.
> > So, I cannot just extend it to suit my devices needs and I don't see
> > how can I extend it in
> > a generic manner so that it controls the pins directly via a regmap
> > for example, especially since
> > each switch has a different number of SFP ports and thus pins and a
> > different register layout.
> >
> > I have added Andrew Lunn as he is one of the maintainers of PHYLIB
> > under which the SFP driver
> > is, he may have some input on how to proceed with this.
> >
> > I honestly think that we have some kind of misunderstanding here and
> > look forward to resolving it.
>
> Hi Robert
>
> Can you describe your hardware and regmap in a bit more detail. What
> do these registers look like? How do they map to the SFP cage pins?

Hi Andrew,
This board is simple as it only has 4 SFP ports so they have split the
respective
pins into individual registers per their purpose.

So TX disable pins have their own 8bit register and they map pins
using individual bits.
This is how the register looks:
+-----+---------------+-----+-------------------+---------------+
| Bit |     Name      | R/W |    Description    | Default value |
+-----+---------------+-----+-------------------+---------------+
| 7:4 | Reserved         | R/W | Not used                |     0 |
| 3   | TX_Disable_52 | R/W | Enable/disable       |     0 |
| 2   | TX_Disable_51 | R/W | SFP TX transmiter |     0 |
| 1   | TX_Disable_50 | R/W | 1 = TX off               |     0 |
| 0   | TX_Disable_49 | R/W | 0 = TX on               |     0 |
+-----+---------------+-----+-------------------+---------------+

Presence and LOS pins also have their respective registers in
the same format.
So you can see that the register bits map directly to the SFP cage pins.

Regards,
Robert
>
>           Andrew



-- 
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
10000 Zagreb, Croatia
Email: robert.marko@...tura.hr
Web: www.sartura.hr