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Message-ID: <20211019110443.GE13251@willie-the-truck>
Date: Tue, 19 Oct 2021 12:04:43 +0100
From: Will Deacon <will@...nel.org>
To: Suzuki K Poulose <suzuki.poulose@....com>
Cc: mathieu.poirier@...aro.org, catalin.marinas@....com,
anshuman.khandual@....com, mike.leach@...aro.org,
leo.yan@...aro.org, maz@...nel.org, coresight@...ts.linaro.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Mark Rutland <mark.rutland@....com>
Subject: Re: [PATCH v5 02/15] arm64: errata: Add detection for TRBE overwrite
in FILL mode
On Thu, Oct 14, 2021 at 11:31:12PM +0100, Suzuki K Poulose wrote:
> Arm Neoverse-N2 and the Cortex-A710 cores are affected
> by a CPU erratum where the TRBE will overwrite the trace buffer
> in FILL mode. The TRBE doesn't stop (as expected in FILL mode)
> when it reaches the limit and wraps to the base to continue
> writing upto 3 cache lines. This will overwrite any trace that
> was written previously.
>
> Add the Neoverse-N2 erratumi(#2139208) and Cortex-A710 erratum
> (#2119858) to the detection logic.
Weird typo and double space in this sentence.
Will
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