lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20211019115205.1516311-2-horatiu.vultur@microchip.com>
Date:   Tue, 19 Oct 2021 13:52:04 +0200
From:   Horatiu Vultur <horatiu.vultur@...rochip.com>
To:     <p.zabel@...gutronix.de>, <robh+dt@...nel.org>
CC:     <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        "Horatiu Vultur" <horatiu.vultur@...rochip.com>
Subject: [PATCH 1/2] dt-bindings: reset: lan966x phy reset driver bindings

Document the lan966x phy reset device driving bindings.
It is using register access for the internal PHYs and toggles
GPIO for external PHYs.

Signed-off-by: Horatiu Vultur <horatiu.vultur@...rochip.com>
---
 .../bindings/reset/lan966x-phy,rst.yaml       | 53 +++++++++++++++++++
 1 file changed, 53 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/lan966x-phy,rst.yaml

diff --git a/Documentation/devicetree/bindings/reset/lan966x-phy,rst.yaml b/Documentation/devicetree/bindings/reset/lan966x-phy,rst.yaml
new file mode 100644
index 000000000000..35a32458cafe
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/lan966x-phy,rst.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/lan966x-phy,rst.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microchip Lan966x PHY Reset
+
+maintainers:
+  - Horatiu Vultur <horatiu.vultur@...rochip.com>
+
+description: |
+  The Microchip Lan966x Switch provides 2 internal PHY which needs to be
+  released from reset before they can be accessed. Also it might have external
+  PHYs which requires to toggle a GPIO before the access to the PHYs.
+
+properties:
+  $nodename:
+    pattern: "^phy-reset@[0-9a-f]+$"
+
+  compatible:
+    const: microchip,lan966x-phy-reset
+
+  reg:
+    items:
+      - description: internal phy reset registers
+
+  reg-names:
+    const: phy
+
+  "#reset-cells":
+    const: 1
+
+  external-phy-reset-gpios:
+    description: used for release of reset of the external PHY
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    phy_reset: phy-reset@...10010 {
+        compatible = "microchip,lan966x-phy-reset";
+        reg = <0xe2010010 0x14>;
+        reg-names = "phy";
+        #reset-cells = <1>;
+    };
-- 
2.33.0

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ