lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Message-ID: <163465058366.25758.3434027960137456326.tip-bot2@tip-bot2> Date: Tue, 19 Oct 2021 13:36:23 -0000 From: "tip-bot2 for Tom Lendacky" <tip-bot2@...utronix.de> To: linux-tip-commits@...r.kernel.org Cc: Tom Lendacky <thomas.lendacky@....com>, Borislav Petkov <bp@...e.de>, "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>, <stable@...r.kernel.org>, x86@...nel.org, linux-kernel@...r.kernel.org Subject: [tip: x86/sev] x86/sme: Use #define USE_EARLY_PGTABLE_L5 in mem_encrypt_identity.c The following commit has been merged into the x86/sev branch of tip: Commit-ID: e7d445ab26db833d6640d4c9a08bee176777cc82 Gitweb: https://git.kernel.org/tip/e7d445ab26db833d6640d4c9a08bee176777cc82 Author: Tom Lendacky <thomas.lendacky@....com> AuthorDate: Fri, 15 Oct 2021 12:24:16 -05:00 Committer: Borislav Petkov <bp@...e.de> CommitterDate: Tue, 19 Oct 2021 14:07:17 +02:00 x86/sme: Use #define USE_EARLY_PGTABLE_L5 in mem_encrypt_identity.c When runtime support for converting between 4-level and 5-level pagetables was added to the kernel, the SME code that built pagetables was updated to use the pagetable functions, e.g. p4d_offset(), etc., in order to simplify the code. However, the use of the pagetable functions in early boot code requires the use of the USE_EARLY_PGTABLE_L5 #define in order to ensure that the proper definition of pgtable_l5_enabled() is used. Without the #define, pgtable_l5_enabled() is #defined as cpu_feature_enabled(X86_FEATURE_LA57). In early boot, the CPU features have not yet been discovered and populated, so pgtable_l5_enabled() will return false even when 5-level paging is enabled. This causes the SME code to always build 4-level pagetables to perform the in-place encryption. If 5-level paging is enabled, switching to the SME pagetables results in a page-fault that kills the boot. Adding the #define results in pgtable_l5_enabled() using the __pgtable_l5_enabled variable set in early boot and the SME code building pagetables for the proper paging level. Fixes: aad983913d77 ("x86/mm/encrypt: Simplify sme_populate_pgd() and sme_populate_pgd_large()") Signed-off-by: Tom Lendacky <thomas.lendacky@....com> Signed-off-by: Borislav Petkov <bp@...e.de> Acked-by: Kirill A. Shutemov <kirill.shutemov@...ux.intel.com> Cc: <stable@...r.kernel.org> # 4.18.x Link: https://lkml.kernel.org/r/2cb8329655f5c753905812d951e212022a480475.1634318656.git.thomas.lendacky@amd.com --- arch/x86/mm/mem_encrypt_identity.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/x86/mm/mem_encrypt_identity.c b/arch/x86/mm/mem_encrypt_identity.c index 470b202..700ce8f 100644 --- a/arch/x86/mm/mem_encrypt_identity.c +++ b/arch/x86/mm/mem_encrypt_identity.c @@ -27,6 +27,15 @@ #undef CONFIG_PARAVIRT_XXL #undef CONFIG_PARAVIRT_SPINLOCKS +/* + * This code runs before CPU feature bits are set. By default, the + * pgtable_l5_enabled() function uses bit X86_FEATURE_LA57 to determine if + * 5-level paging is active, so that won't work here. USE_EARLY_PGTABLE_L5 + * is provided to handle this situation and, instead, use a variable that + * has been set by the early boot code. + */ +#define USE_EARLY_PGTABLE_L5 + #include <linux/kernel.h> #include <linux/mm.h> #include <linux/mem_encrypt.h>
Powered by blists - more mailing lists