linux-kernel - [irqchip: irq/irqchip-next] genirq: Export irq_gc_{unmask_enable,mask_disable}

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 20 Oct 2021 21:12:13 -0000
From:   "irqchip-bot for Florian Fainelli" <tip-bot2@...utronix.de>
To:     linux-kernel@...r.kernel.org
Cc:     Florian Fainelli <f.fainelli@...il.com>,
        Marc Zyngier <maz@...nel.org>, tglx@...utronix.de
Subject: [irqchip: irq/irqchip-next] genirq: Export
 irq_gc_{unmask_enable,mask_disable}_reg

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID:     fcd0f63dec4abc281988ac08b83ca3ae6946c13b
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/fcd0f63dec4abc281988ac08b83ca3ae6946c13b
Author:        Florian Fainelli <f.fainelli@...il.com>
AuthorDate:    Wed, 20 Oct 2021 11:48:53 -07:00
Committer:     Marc Zyngier <maz@...nel.org>
CommitterDate: Wed, 20 Oct 2021 20:06:33 +01:00

genirq: Export irq_gc_{unmask_enable,mask_disable}_reg

In order to allow drivers/irqchip/irq-brcmstb-l2.c to be built as a
module we need to export: irq_gc_unmask_enable_reg() and
irq_gc_mask_disable_reg().

Signed-off-by: Florian Fainelli <f.fainelli@...il.com>
Signed-off-by: Marc Zyngier <maz@...nel.org>
Link: https://lore.kernel.org/r/20211020184859.2705451-8-f.fainelli@gmail.com
---
 kernel/irq/generic-chip.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index cc7cdd2..4c011c2 100644
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -44,6 +44,7 @@ void irq_gc_mask_disable_reg(struct irq_data *d)
 	*ct->mask_cache &= ~mask;
 	irq_gc_unlock(gc);
 }
+EXPORT_SYMBOL_GPL(irq_gc_mask_disable_reg);
 
 /**
  * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
@@ -103,6 +104,7 @@ void irq_gc_unmask_enable_reg(struct irq_data *d)
 	*ct->mask_cache |= mask;
 	irq_gc_unlock(gc);
 }
+EXPORT_SYMBOL_GPL(irq_gc_unmask_enable_reg);
 
 /**
  * irq_gc_ack_set_bit - Ack pending interrupt via setting bit