linux-kernel - [PATCH 1/3] ARM: dts: at91: sama7g5: add rtc node

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Message-ID: <20211020094656.3343242-2-claudiu.beznea@microchip.com>
Date:   Wed, 20 Oct 2021 12:46:54 +0300
From:   Claudiu Beznea <claudiu.beznea@...rochip.com>
To:     <nicolas.ferre@...rochip.com>, <alexandre.belloni@...tlin.com>,
        <ludovic.desroches@...rochip.com>, <robh+dt@...nel.org>
CC:     <linux-arm-kernel@...ts.infradead.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        Eugen Hristev <eugen.hristev@...rochip.com>,
        Claudiu Beznea <claudiu.beznea@...rochip.com>
Subject: [PATCH 1/3] ARM: dts: at91: sama7g5: add rtc node

From: Eugen Hristev <eugen.hristev@...rochip.com>

Add RTC node.

Signed-off-by: Eugen Hristev <eugen.hristev@...rochip.com>
[claudiu.beznea: add sama7g5 compatible as the IP has 2 extra registers
 compared with sam9x60]
Signed-off-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
---
 arch/arm/boot/dts/sama7g5.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index 6a9d74a9e1ac..e16a337fd100 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -152,6 +152,13 @@ gpbr: gpbr@...1d060 {
 			reg = <0xe001d060 0x48>;
 		};
 
+		rtc: rtc@...1d0a8 {
+			compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc";
+			reg = <0xe001d0a8 0x30>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk32k 1>;
+		};
+
 		ps_wdt: watchdog@...1d180 {
 			compatible = "microchip,sama7g5-wdt";
 			reg = <0xe001d180 0x24>;
-- 
2.25.1