linux-kernel - [PATCH 3/3] arm64: dts: s32g2: add USDHC support

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Message-ID: <20211021071333.32485-4-clin@suse.com>
Date:   Thu, 21 Oct 2021 15:13:33 +0800
From:   Chester Lin <clin@...e.com>
To:     s32@....com, Andreas Färber <afaerber@...e.de>,
        Matthias Brugger <mbrugger@...e.com>,
        devicetree@...r.kernel.org
CC:     Ulf Hansson <ulf.hansson@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        Fabio Estevam <festevam@...il.com>,
        NXP Linux Team <linux-imx@....com>,
        linux-mmc@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org,
        Radu Nicolae Pirea <radu-nicolae.pirea@....nxp.com>,
        Dong Aisheng <aisheng.dong@....com>,
        BOUGH CHEN <haibo.chen@....com>,
        "Ivan T . Ivanov" <iivanov@...e.de>,
        "Lee, Chun-Yi" <jlee@...e.com>, Chester Lin <clin@...e.com>
Subject: [PATCH 3/3] arm64: dts: s32g2: add USDHC support

Add a mmc node to support USDHC on NXP S32G2 platforms.

Signed-off-by: Chester Lin <clin@...e.com>
---
 arch/arm64/boot/dts/freescale/s32g2.dtsi      | 32 +++++++++++++++++++
 .../arm64/boot/dts/freescale/s32g274a-evb.dts |  4 +++
 .../boot/dts/freescale/s32g274a-rdb2.dts      |  4 +++
 3 files changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 59ea8a25aa4c..19e2e2561374 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -79,6 +79,26 @@ psci {
 		};
 	};
 
+	clocks {
+		usdhc_clk_module: usdhc_clk_module {
+			compatible = "fixed-clock";
+			clock-frequency = <133333333>;
+			#clock-cells = <0>;
+		};
+
+		usdhc_clk_ahb: usdhc_clk_ahb {
+			compatible = "fixed-clock";
+			clock-frequency = <400000000>;
+			#clock-cells = <0>;
+		};
+
+		usdhc_clk_core: usdhc_clk_core {
+			compatible = "fixed-clock";
+			clock-frequency = <400000000>;
+			#clock-cells = <0>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -109,6 +129,18 @@ uart2: serial@...bc000 {
 			status = "disabled";
 		};
 
+		usdhc0: mmc@...f0000 {
+			compatible = "nxp,s32g2-usdhc";
+			reg = <0x402f0000 0x1000>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			bus-width = <8>;
+			clocks = <&usdhc_clk_module>, <&usdhc_clk_ahb>,
+				 <&usdhc_clk_core>;
+			clock-names = "ipg", "ahb", "per";
+			no-1-8-v;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@...00000 {
 			compatible = "arm,gic-v3";
 			reg = <0x50800000 0x10000>,
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
index 9118d8d2ee01..89428f1883d9 100644
--- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
+++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
@@ -32,3 +32,7 @@ memory@...00000 {
 &uart0 {
 	status = "okay";
 };
+
+&usdhc0 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
index e05ee854cdf5..30eae51121de 100644
--- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
+++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
@@ -38,3 +38,7 @@ &uart0 {
 &uart1 {
 	status = "okay";
 };
+
+&usdhc0 {
+	status = "okay";
+};
-- 
2.30.0