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Message-ID: <20211021123021.9602-2-pshete@nvidia.com>
Date: Thu, 21 Oct 2021 18:00:21 +0530
From: Prathamesh Shete <pshete@...dia.com>
To: <linus.walleij@...aro.org>, <bgolaszewski@...libre.com>,
<thierry.reding@...il.com>, <jonathanh@...dia.com>,
<linux-gpio@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
CC: <smangipudi@...dia.com>, <pshete@...dia.com>
Subject: [PATCH 2/2] gpio: tegra186: Add support for Tegra234 gpio
Add support for the Tegra234 GPIO bank configuration.
Signed-off-by: Prathamesh Shete <pshete@...dia.com>
---
drivers/gpio/gpio-tegra186.c | 74 ++++++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c
index d38980b9923a..edcc91b35e1e 100644
--- a/drivers/gpio/gpio-tegra186.c
+++ b/drivers/gpio/gpio-tegra186.c
@@ -14,6 +14,7 @@
#include <dt-bindings/gpio/tegra186-gpio.h>
#include <dt-bindings/gpio/tegra194-gpio.h>
+#include <dt-bindings/gpio/tegra234-gpio.h>
/* security registers */
#define TEGRA186_GPIO_CTL_SCR 0x0c
@@ -877,6 +878,73 @@ static const struct tegra_gpio_soc tegra194_aon_soc = {
.instance = 1,
};
+#define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
+ [TEGRA234_MAIN_GPIO_PORT_##_name] = { \
+ .name = #_name, \
+ .bank = _bank, \
+ .port = _port, \
+ .pins = _pins, \
+ }
+
+static const struct tegra_gpio_port tegra234_main_ports[] = {
+ TEGRA234_MAIN_GPIO_PORT(A, 0, 0, 8),
+ TEGRA234_MAIN_GPIO_PORT(B, 0, 3, 1),
+ TEGRA234_MAIN_GPIO_PORT(C, 5, 1, 8),
+ TEGRA234_MAIN_GPIO_PORT(D, 5, 2, 4),
+ TEGRA234_MAIN_GPIO_PORT(E, 5, 3, 8),
+ TEGRA234_MAIN_GPIO_PORT(F, 5, 4, 6),
+ TEGRA234_MAIN_GPIO_PORT(G, 4, 0, 8),
+ TEGRA234_MAIN_GPIO_PORT(H, 4, 1, 8),
+ TEGRA234_MAIN_GPIO_PORT(I, 4, 2, 7),
+ TEGRA234_MAIN_GPIO_PORT(J, 5, 0, 6),
+ TEGRA234_MAIN_GPIO_PORT(K, 3, 0, 8),
+ TEGRA234_MAIN_GPIO_PORT(L, 3, 1, 4),
+ TEGRA234_MAIN_GPIO_PORT(M, 2, 0, 8),
+ TEGRA234_MAIN_GPIO_PORT(N, 2, 1, 8),
+ TEGRA234_MAIN_GPIO_PORT(P, 2, 2, 8),
+ TEGRA234_MAIN_GPIO_PORT(Q, 2, 3, 8),
+ TEGRA234_MAIN_GPIO_PORT(R, 2, 4, 6),
+ TEGRA234_MAIN_GPIO_PORT(X, 1, 0, 8),
+ TEGRA234_MAIN_GPIO_PORT(Y, 1, 1, 8),
+ TEGRA234_MAIN_GPIO_PORT(Z, 1, 2, 8),
+ TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8),
+ TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4),
+ TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2),
+ TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4),
+ TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8)
+};
+
+static const struct tegra_gpio_soc tegra234_main_soc = {
+ .num_ports = ARRAY_SIZE(tegra234_main_ports),
+ .ports = tegra234_main_ports,
+ .name = "tegra234-gpio",
+ .instance = 0,
+};
+
+#define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \
+ [TEGRA234_AON_GPIO_PORT_##_name] = { \
+ .name = #_name, \
+ .bank = _bank, \
+ .port = _port, \
+ .pins = _pins, \
+ }
+
+static const struct tegra_gpio_port tegra234_aon_ports[] = {
+ TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8),
+ TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4),
+ TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8),
+ TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3),
+ TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8),
+ TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1)
+};
+
+static const struct tegra_gpio_soc tegra234_aon_soc = {
+ .num_ports = ARRAY_SIZE(tegra234_aon_ports),
+ .ports = tegra234_aon_ports,
+ .name = "tegra234-gpio-aon",
+ .instance = 1,
+};
+
static const struct of_device_id tegra186_gpio_of_match[] = {
{
.compatible = "nvidia,tegra186-gpio",
@@ -890,6 +958,12 @@ static const struct of_device_id tegra186_gpio_of_match[] = {
}, {
.compatible = "nvidia,tegra194-gpio-aon",
.data = &tegra194_aon_soc
+ }, {
+ .compatible = "nvidia,tegra234-gpio",
+ .data = &tegra234_main_soc
+ }, {
+ .compatible = "nvidia,tegra234-gpio-aon",
+ .data = &tegra234_aon_soc
}, {
/* sentinel */
}
--
2.17.1
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