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Date:   Thu, 21 Oct 2021 20:37:26 +0530
From:   Naveen Naidu <naveennaidu479@...il.com>
To:     bhelgaas@...gle.com
Cc:     Naveen Naidu <naveennaidu479@...il.com>,
        linux-kernel-mentees@...ts.linuxfoundation.org,
        linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-hyperv@...r.kernel.org,
        linux-mediatek@...ts.infradead.org, linuxppc-dev@...ts.ozlabs.org,
        linux-renesas-soc@...r.kernel.org,
        linux-rockchip@...ts.infradead.org,
        linux-samsung-soc@...r.kernel.org, Rob Herring <robh@...nel.org>,
        Pali Rohár <pali@...nel.org>,
        skhan@...uxfoundation.org, Robert Richter <rric@...nel.org>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Krzysztof Wilczyński <kw@...ux.com>,
        Ray Jui <rjui@...adcom.com>,
        Scott Branden <sbranden@...adcom.com>,
        bcm-kernel-feedback-list@...adcom.com (maintainer:BROADCOM IPROC ARM
        ARCHITECTURE), Ryder Lee <ryder.lee@...iatek.com>,
        Jianjun Wang <jianjun.wang@...iatek.com>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Jingoo Han <jingoohan1@...il.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
        Shawn Guo <shawn.guo@...aro.org>,
        Xiaowei Song <songxiaowei@...ilicon.com>,
        Binghui Wang <wangbinghui@...ilicon.com>,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        Joyce Ooi <joyce.ooi@...el.com>,
        Marek Vasut <marek.vasut+renesas@...il.com>,
        Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
        Shawn Lin <shawn.lin@...k-chips.com>,
        Heiko Stuebner <heiko@...ech.de>,
        Nirmal Patel <nirmal.patel@...ux.intel.com>,
        Jonathan Derrick <jonathan.derrick@...ux.dev>,
        Kuppuswamy Sathyanarayanan 
        <sathyanarayanan.kuppuswamy@...ux.intel.com>,
        Lukas Wunner <lukas@...ner.de>,
        Amey Narkhede <ameynarkhede03@...il.com>,
        Russell Currey <ruscur@...sell.cc>,
        "Oliver O'Halloran" <oohall@...il.com>,
        Sean V Kelley <sean.v.kelley@...el.com>,
        Qiuxu Zhuo <qiuxu.zhuo@...el.com>,
        Marc Zyngier <maz@...nel.org>,
        "K. Y. Srinivasan" <kys@...rosoft.com>,
        Haiyang Zhang <haiyangz@...rosoft.com>,
        Stephen Hemminger <sthemmin@...rosoft.com>,
        Wei Liu <wei.liu@...nel.org>, Dexuan Cui <decui@...rosoft.com>,
        Toan Le <toan@...amperecomputing.com>
Subject: [PATCH v3 01/25] PCI: Add PCI_ERROR_RESPONSE and it's related definitions

An MMIO read from a PCI device that doesn't exist or doesn't respond
causes a PCI error.  There's no real data to return to satisfy the
CPU read, so most hardware fabricates ~0 data.

Add a PCI_ERROR_RESPONSE definition for that and use it where
appropriate to make these checks consistent and easier to find.

Also add helper definitions SET_PCI_ERROR_RESPONSE and
RESPONSE_IS_PCI_ERROR to make the code more readable.

Suggested-by: Bjorn Helgaas <bhelgaas@...gle.com>
Signed-off-by: Naveen Naidu <naveennaidu479@...il.com>
---
 include/linux/pci.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/include/linux/pci.h b/include/linux/pci.h
index cd8aa6fce204..689c8277c584 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -154,6 +154,15 @@ enum pci_interrupt_pin {
 /* The number of legacy PCI INTx interrupts */
 #define PCI_NUM_INTX	4
 
+/*
+ * Reading from a device that doesn't respond typically returns ~0.  A
+ * successful read from a device may also return ~0, so you need additional
+ * information to reliably identify errors.
+ */
+#define PCI_ERROR_RESPONSE     (~0ULL)
+#define SET_PCI_ERROR_RESPONSE(val)    (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE))
+#define RESPONSE_IS_PCI_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE))
+
 /*
  * pci_power_t values must match the bits in the Capabilities PME_Support
  * and Control/Status PowerState fields in the Power Management capability.
-- 
2.25.1

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