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Date:   Thu, 21 Oct 2021 17:34:10 +0200
From:   Arnd Bergmann <arnd@...db.de>
To:     Paweł Anikiel <pan@...ihalf.com>
Cc:     Arnd Bergmann <arnd@...db.de>, Olof Johansson <olof@...om.net>,
        SoC Team <soc@...nel.org>, Rob Herring <robh+dt@...nel.org>,
        Dinh Nguyen <dinguyen@...nel.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        DTML <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        upstream@...ihalf.com, Marcin Wojtas <mw@...ihalf.com>,
        Konrad Adamczyk <ka@...ihalf.com>,
        Jacek Majkowski <jam@...ihalf.com>,
        Tomasz Nowicki <tn@...ihalf.com>,
        Alexandru Stan <amstan@...gle.com>,
        Joanna Brozek <jbrozek@...micro.com>,
        Mariusz Glebocki <mglebocki@...micro.com>,
        Tomasz Gorochowik <tgorochowik@...micro.com>,
        Maciej Mikunda <mmikunda@...micro.com>
Subject: Re: [PATCH v5 1/1] dts: socfpga: Add Mercury+ AA1 devicetree

On Thu, Oct 21, 2021 at 5:17 PM Paweł Anikiel <pan@...ihalf.com> wrote:
>
> Add support for the Mercury+ AA1 module for Arria 10 SoC FPGA.
>
> Signed-off-by: Paweł Anikiel <pan@...ihalf.com>
> Signed-off-by: Joanna Brozek <jbrozek@...micro.com>
> Signed-off-by: Mariusz Glebocki <mglebocki@...micro.com>
> Signed-off-by: Tomasz Gorochowik <tgorochowik@...micro.com>
> Signed-off-by: Maciej Mikunda <mmikunda@...micro.com>

Thank you for the respin, looks good to me now.

Reviewed-by: Arnd Bergmann <arnd@...db.de>

Dinh, are you planning to pick this up into your socfpga tree, or
should I apply it directly to the soc tree this time?

        Arnd

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