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Message-ID: <AS8PR04MB8676F8987117D03875869B868C809@AS8PR04MB8676.eurprd04.prod.outlook.com>
Date: Fri, 22 Oct 2021 02:04:41 +0000
From: Richard Zhu <hongxing.zhu@....com>
To: Rob Herring <robh@...nel.org>
CC: "l.stach@...gutronix.de" <l.stach@...gutronix.de>,
"tharvey@...eworks.com" <tharvey@...eworks.com>,
"kishon@...com" <kishon@...com>,
"vkoul@...nel.org" <vkoul@...nel.org>,
"galak@...nel.crashing.org" <galak@...nel.crashing.org>,
"shawnguo@...nel.org" <shawnguo@...nel.org>,
"linux-phy@...ts.infradead.org" <linux-phy@...ts.infradead.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"kernel@...gutronix.de" <kernel@...gutronix.de>,
dl-linux-imx <linux-imx@....com>
Subject: RE: [PATCH v3 6/9] dt-bindings: imx6q-pcie: Add PHY phandles and name
properties
> -----Original Message-----
> From: Rob Herring <robh@...nel.org>
> Sent: Tuesday, October 19, 2021 3:18 AM
> To: Richard Zhu <hongxing.zhu@....com>
> Cc: l.stach@...gutronix.de; tharvey@...eworks.com; kishon@...com;
> vkoul@...nel.org; galak@...nel.crashing.org; shawnguo@...nel.org;
> linux-phy@...ts.infradead.org; devicetree@...r.kernel.org;
> linux-arm-kernel@...ts.infradead.org; linux-kernel@...r.kernel.org;
> kernel@...gutronix.de; dl-linux-imx <linux-imx@....com>
> Subject: Re: [PATCH v3 6/9] dt-bindings: imx6q-pcie: Add PHY phandles and
> name properties
>
> On Tue, Oct 12, 2021 at 04:41:15PM +0800, Richard Zhu wrote:
> > i.MX8MM PCIe has the PHY. Add a PHY phandle and name properties in the
> > binding document.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> > ---
> > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > index 2911e565b260..99d9863a69cd 100644
> > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > @@ -128,6 +128,12 @@ properties:
> > enum: [1, 2, 3, 4]
> > default: 1
> >
> > + phys:
> > + description: Phandle of the Generic PHY to the PCIe PHY.
>
> maxItems: 1
>
> And drop 'description'
[Richard Zhu] Hi Rob:
Do you mean to remove all the description, and just like this?
phys:
maxItems: 1
Ok, got that, would be changed as this one in v4 series later.
Thanks.
Best Regards
Richard Zhu
>
> > +
> > + phy-names:
> > + const: pcie-phy
> > +
> > reset-gpio:
> > description: Should specify the GPIO for controlling the PCI bus
> device
> > reset signal. It's not polarity aware and defaults to
> > active-low reset
> > --
> > 2.25.1
> >
> >
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