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Date:   Sun, 24 Oct 2021 12:58:20 -0300
From:   Fabio Estevam <festevam@...il.com>
To:     Jesse Taube <mr.bossman075@...il.com>
Cc:     NXP Linux Team <linux-imx@....com>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Sascha Hauer <kernel@...gutronix.de>,
        Ulf Hansson <ulf.hansson@...aro.org>,
        Dong Aisheng <aisheng.dong@....com>,
        Stefan Agner <stefan@...er.ch>,
        Linus Walleij <linus.walleij@...aro.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Arnd Bergmann <arnd@...db.de>, Olof Johansson <olof@...om.net>,
        soc@...nel.org, Russell King - ARM Linux <linux@...linux.org.uk>,
        Abel Vesa <abel.vesa@....com>,
        Adrian Hunter <adrian.hunter@...el.com>,
        Jiri Slaby <jirislaby@...nel.org>,
        Giulio Benetti <giulio.benetti@...ettiengineering.com>,
        Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...hiba.co.jp>,
        Leonard Crestez <leonard.crestez@....com>,
        Anson Huang <b20788@...escale.com>,
        Fugang Duan <fugang.duan@....com>,
        linux-clk <linux-clk@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        linux-mmc <linux-mmc@...r.kernel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        linux-serial@...r.kernel.org
Subject: Re: [PATCH 07/13] clk: imx: Add initial support for i.MXRT clock driver

Hi Jesse,

On Sun, Oct 24, 2021 at 12:40 PM Jesse Taube <mr.bossman075@...il.com> wrote:

> +#include "clk.h"
> +#define ANATOP_BASE_ADDR       0x400d8000

This should be retrieved from the device tree

> +       imx_check_clocks(clk, ARRAY_SIZE(clk));
> +       clk_data.clks = clk;
> +       clk_data.clk_num = ARRAY_SIZE(clk);
> +       of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
> +       clk_set_parent(clk[IMXRT1050_CLK_PLL1_BYPASS], clk[IMXRT1050_CLK_PLL1_REF_SEL]);

The clock parent description could be made via device tree.

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