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Message-ID: <YXcup7d6ROmmPCuD@robh.at.kernel.org>
Date: Mon, 25 Oct 2021 17:24:39 -0500
From: Rob Herring <robh@...nel.org>
To: Jim Quinlan <jim2101024@...il.com>
Cc: linux-pci@...r.kernel.org,
Nicolas Saenz Julienne <nsaenz@...nel.org>,
Mark Brown <broonie@...nel.org>,
bcm-kernel-feedback-list@...adcom.com, james.quinlan@...adcom.com,
Florian Fainelli <f.fainelli@...il.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Saenz Julienne <nsaenzjulienne@...e.de>,
"moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE"
<linux-arm-kernel@...ts.infradead.org>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-rpi-kernel@...ts.infradead.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v5 1/6] dt-bindings: PCI: Add bindings for Brcmstb EP
voltage regulators
On Fri, Oct 22, 2021 at 10:06:54AM -0400, Jim Quinlan wrote:
> Similar to the regulator bindings found in "rockchip-pcie-host.txt", this
> allows optional regulators to be attached and controlled by the PCIe RC
> driver. That being said, this driver searches in the DT subnode (the EP
> node, eg pci@0,0) for the regulator property.
>
> The use of a regulator property in the pcie EP subnode such as
> "vpcie12v-supply" depends on a pending pullreq to the pci-bus.yaml
> file at
>
> https://github.com/devicetree-org/dt-schema/pull/54
>
> Signed-off-by: Jim Quinlan <jim2101024@...il.com>
> ---
> .../bindings/pci/brcm,stb-pcie.yaml | 23 +++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> index b9589a0daa5c..fec13e4f6eda 100644
> --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> @@ -154,5 +154,28 @@ examples:
> <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
> brcm,enable-ssc;
> brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
> +
> + /* PCIe bridge */
More specifically, the root port.
> + pci@0,0 {
> + #address-cells = <3>;
> + #size-cells = <2>;
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + device_type = "pci";
> + ranges;
> +
> + /* PCIe endpoint */
> + pci@0,0 {
> + device_type = "pci";
This means this device is a PCI bridge which wouldn't typically be the
endpoint. Is that intended?
> + assigned-addresses = <0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>;
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + compatible = "pci14e4,1688";
> + vpcie3v3-supply = <&vreg7>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges;
> + };
> + };
> };
> };
> --
> 2.17.1
>
>
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