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Date: Mon, 25 Oct 2021 10:17:31 +0100 From: Mark Rutland <mark.rutland@....com> To: Brad Larson <brad@...sando.io> Cc: linux-arm-kernel@...ts.infradead.org, arnd@...db.de, linus.walleij@...aro.org, bgolaszewski@...libre.com, broonie@...nel.org, fancer.lancer@...il.com, adrian.hunter@...el.com, ulf.hansson@...aro.org, olof@...om.net, linux-gpio@...r.kernel.org, linux-spi@...r.kernel.org, linux-mmc@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH v3 11/11] arm64: dts: Add Pensando Elba SoC support Hi, On Sun, Oct 24, 2021 at 06:51:56PM -0700, Brad Larson wrote: > Add Pensando common and Elba SoC specific device nodes > > Signed-off-by: Brad Larson <brad@...sando.io> [...] > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | > + IRQ_TYPE_LEVEL_LOW)>; > + }; The GIC_CPU_MASK_SIMPLE() stuff is meant for GICv2, but as below you have GICv3, where this is not valid, so this should go. Also, beware that GIC_CPU_MASK_SIMPLE(1) means a single CPU, which doesn't mak sense for the 16 CPUs you have. > + gic: interrupt-controller@...000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + interrupt-controller; > + reg = <0x0 0x800000 0x0 0x200000>, /* GICD */ > + <0x0 0xa00000 0x0 0x200000>; /* GICR */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + > + gic_its: msi-controller@...000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + #msi-cells = <1>; > + reg = <0x0 0x820000 0x0 0x10000>; > + socionext,synquacer-pre-its = > + <0xc00000 0x1000000>; > + }; > + }; Is there any shared lineage with Synquacer? The commit message didn't describe this quirk. Thanks, Mark.
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