[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <YXiQ6Q8zhY+RZRue@robh.at.kernel.org>
Date: Tue, 26 Oct 2021 18:36:09 -0500
From: Rob Herring <robh@...nel.org>
To: Xin Ji <xji@...logixsemi.com>
Cc: dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org,
robh+dt@...nel.org, hsinyi@...omium.org, zhenli@...logixsemi.com,
mripard@...nel.org, airlied@...ux.ie, span@...logixsemi.com,
sam@...nborg.org, linux-kernel@...r.kernel.org,
bliang@...logixsemi.com, drinkcat@...gle.com, broonie@...nel.org,
ricardo.canuelo@...labora.com, daniel@...ll.ch,
laurent.pinchart+renesas@...asonboard.com
Subject: Re: [PATCH v11 1/4] dt-bindings:drm/bridge:anx7625:add vendor define
On Mon, 18 Oct 2021 11:03:23 +0800, Xin Ji wrote:
> Add 'bus-type' and 'data-lanes' define for port0. Add DP tx lane0,
> lane1 swing register setting array, and audio enable flag.
>
> The device which cannot pass DP tx PHY CTS caused by long PCB trace or
> embedded MUX, adjusting ANX7625 PHY parameters can pass the CTS test. The
> adjusting type include Pre-emphasis, Vp-p, Rterm(Resistor Termination)
> and Rsel(Driven Strength). Each lane has maximum 20 registers for
> these settings.
>
> Signed-off-by: Xin Ji <xji@...logixsemi.com>
> ---
> .../display/bridge/analogix,anx7625.yaml | 65 ++++++++++++++++++-
> 1 file changed, 63 insertions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring <robh@...nel.org>
Powered by blists - more mailing lists