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Message-ID: <e96dc19c-b289-7e5d-4a0a-4609214a9818@intel.com>
Date: Tue, 26 Oct 2021 08:54:46 -0700
From: Dave Hansen <dave.hansen@...el.com>
To: Nadav Amit <nadav.amit@...il.com>, linux-mm@...ck.org
Cc: linux-kernel@...r.kernel.org, Nadav Amit <namit@...are.com>,
Andi Kleen <ak@...ux.intel.com>,
Andrea Arcangeli <aarcange@...hat.com>,
Andrew Cooper <andrew.cooper3@...rix.com>,
Andrew Morton <akpm@...ux-foundation.org>,
Andy Lutomirski <luto@...nel.org>,
Dave Hansen <dave.hansen@...ux.intel.com>,
Peter Xu <peterx@...hat.com>,
Peter Zijlstra <peterz@...radead.org>,
Thomas Gleixner <tglx@...utronix.de>,
Will Deacon <will@...nel.org>, Yu Zhao <yuzhao@...gle.com>,
Nick Piggin <npiggin@...il.com>, x86@...nel.org
Subject: Re: [PATCH v2 1/5] x86: Detection of Knights Landing A/D leak
On 10/21/21 5:21 AM, Nadav Amit wrote:
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -296,6 +296,11 @@ static void early_init_intel(struct cpuinfo_x86 *c)
> }
> }
>
> + if (c->x86_model == 87) {
> + pr_info_once("Enabling PTE leaking workaround\n");
> + set_cpu_bug(c, X86_BUG_PTE_LEAK);
> + }
Please take a look at:
arch/x86/include/asm/intel-family.h
specifically:
#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
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