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Message-ID: <bfa95168-c729-9b81-e87c-f49754cc06fc@intel.com>
Date: Tue, 26 Oct 2021 09:09:21 -0700
From: Dave Hansen <dave.hansen@...el.com>
To: Nadav Amit <nadav.amit@...il.com>,
Andrew Morton <akpm@...ux-foundation.org>
Cc: Linux-MM <linux-mm@...ck.org>, LKML <linux-kernel@...r.kernel.org>,
Andi Kleen <ak@...ux.intel.com>,
Andrea Arcangeli <aarcange@...hat.com>,
Andrew Cooper <andrew.cooper3@...rix.com>,
Andy Lutomirski <luto@...nel.org>,
Dave Hansen <dave.hansen@...ux.intel.com>,
Peter Xu <peterx@...hat.com>,
Peter Zijlstra <peterz@...radead.org>,
Thomas Gleixner <tglx@...utronix.de>,
Will Deacon <will@...nel.org>, Yu Zhao <yuzhao@...gle.com>,
Nick Piggin <npiggin@...il.com>, x86@...nel.org
Subject: Re: [PATCH v2 0/5] mm/mprotect: avoid unnecessary TLB flushes
On 10/22/21 2:58 PM, Nadav Amit wrote:
>> [1/5] appears to be a significant fix which should probably be
>> backported into -stable kernels. If you agree with this then I suggest
>> it be prepared as a standalone patch, separate from the other four
>> patches. With a cc:stable.
>
> There is no functionality bug in the kernel. The Knights Landing bug
> was circumvented eventually by changing the swap entry structure so
> the access/dirty bits would not overlap with the swap entry data.
Yeah, it was a significant issue, but we fixed it in here:
> commit 00839ee3b299303c6a5e26a0a2485427a3afcbbf
> Author: Dave Hansen <dave.hansen@...ux.intel.com>
> Date: Thu Jul 7 17:19:11 2016 -0700
>
> x86/mm: Move swap offset/type up in PTE to work around erratum
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