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Message-Id: <20211027103352.8879-5-sshivamurthy@micron.com>
Date: Wed, 27 Oct 2021 10:33:52 +0000
From: shiva.linuxworks@...il.com
To: tudor.ambarus@...rochip.com, michael@...le.cc, p.yadav@...com,
miquel.raynal@...tlin.com, richard@....at, vigneshr@...com
Cc: linux-mtd@...ts.infradead.org, linux-kernel@...r.kernel.org,
Shivamurthy Shastri <sshivamurthy@...ron.com>
Subject: [PATCH 4/4] mtd: spi-nor: micron-st: add mt25qu128abb and mt25ql128abb
From: Shivamurthy Shastri <sshivamurthy@...ron.com>
Added new Micron SPI NOR flashes to structure flash_info, which supports
advanced protection and security features.
Signed-off-by: Shivamurthy Shastri <sshivamurthy@...ron.com>
---
drivers/mtd/spi-nor/micron-st.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index b5d82e85fb92..2bebd76b091a 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -158,10 +158,17 @@ static const struct flash_info st_parts[] = {
SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128,
SECT_4K | SPI_NOR_QUAD_READ) },
+ { "mt25qu128abb", INFO6(0x20bb18, 0x12008c, 64 * 1024, 256,
+ SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
+ SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256,
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
+ { "mt25ql128abb", INFO6(0x20ba18, 0x12008c, 64 * 1024, 256,
+ SECT_4K | USE_FSR | SPI_NOR_HAS_LOCK |
+ SPI_NOR_QUAD_READ) },
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256,
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512,
--
2.25.1
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