| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Wed, 27 Oct 2021 12:44:19 +0200
From: Eric Auger <eric.auger@...hat.com>
To: eric.auger.pro@...il.com, eric.auger@...hat.com,
iommu@...ts.linux-foundation.org, linux-kernel@...r.kernel.org,
kvm@...r.kernel.org, kvmarm@...ts.cs.columbia.edu, joro@...tes.org,
will@...nel.org, robin.murphy@....com, jean-philippe@...aro.org,
zhukeqian1@...wei.com
Cc: alex.williamson@...hat.com, jacob.jun.pan@...ux.intel.com,
yi.l.liu@...el.com, kevin.tian@...el.com, ashok.raj@...el.com,
maz@...nel.org, peter.maydell@...aro.org, vivek.gautam@....com,
shameerali.kolothum.thodi@...wei.com, wangxingang5@...wei.com,
jiangkunkun@...wei.com, yuzenghui@...wei.com,
nicoleotsuka@...il.com, chenxiang66@...ilicon.com,
sumitg@...dia.com, nicolinc@...dia.com, vdumpa@...dia.com,
zhangfei.gao@...aro.org, zhangfei.gao@...il.com,
lushenming@...wei.com, vsethi@...dia.com
Subject: [RFC v16 0/9] SMMUv3 Nested Stage Setup (IOMMU part)
This series brings the IOMMU part of HW nested paging support
in the SMMUv3.
The SMMUv3 driver is adapted to support 2 nested stages.
The IOMMU API is extended to convey the guest stage 1
configuration and the hook is implemented in the SMMUv3 driver.
This allows the guest to own the stage 1 tables and context
descriptors (so-called PASID table) while the host owns the
stage 2 tables and main configuration structures (STE).
This work mainly is provided for test purpose as the upper
layer integration is under rework and bound to be based on
/dev/iommu instead of VFIO tunneling. In this version we also get
rid of the MSI BINDING ioctl, assuming the guest enforces
flat mapping of host IOVAs used to bind physical MSI doorbells.
In the current QEMU integration this is achieved by exposing
RMRs to the guest, using Shameer's series [1]. This approach
is RFC as the IORT spec is not really meant to do that
(single mapping flag limitation).
Best Regards
Eric
This series (Host) can be found at:
https://github.com/eauger/linux/tree/v5.15-rc7-nested-v16
This includes a rebased VFIO integration (although not meant
to be upstreamed)
Guest kernel branch can be found at:
https://github.com/eauger/linux/tree/shameer_rmrr_v7
featuring [1]
QEMU integration (still based on VFIO and exposing RMRs)
can be found at:
https://github.com/eauger/qemu/tree/v6.1.0-rmr-v2-nested_smmuv3_v10
(use iommu=nested-smmuv3 ARM virt option)
Guest dependency:
[1] [PATCH v7 0/9] ACPI/IORT: Support for IORT RMR node
History:
v15 -> v16:
- guest RIL must support RIL
- additional checks in the cache invalidation hook
- removal of the MSI BINDING ioctl (tentative replacement
by RMRs)
Eric Auger (9):
iommu: Introduce attach/detach_pasid_table API
iommu: Introduce iommu_get_nesting
iommu/smmuv3: Allow s1 and s2 configs to coexist
iommu/smmuv3: Get prepared for nested stage support
iommu/smmuv3: Implement attach/detach_pasid_table
iommu/smmuv3: Allow stage 1 invalidation with unmanaged ASIDs
iommu/smmuv3: Implement cache_invalidate
iommu/smmuv3: report additional recoverable faults
iommu/smmuv3: Disallow nested mode in presence of HW MSI regions
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 383 ++++++++++++++++++--
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 14 +-
drivers/iommu/arm/arm-smmu/arm-smmu.c | 8 +
drivers/iommu/intel/iommu.c | 13 +
drivers/iommu/iommu.c | 79 ++++
include/linux/iommu.h | 35 ++
include/uapi/linux/iommu.h | 54 +++
7 files changed, 548 insertions(+), 38 deletions(-)
--
2.26.3
Powered by blists - more mailing lists