linux-kernel - [RFC v16 9/9] iommu/smmuv3: Disallow nested mode in presence of HW MSI regions

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Message-Id: <20211027104428.1059740-10-eric.auger@redhat.com>
Date:   Wed, 27 Oct 2021 12:44:28 +0200
From:   Eric Auger <eric.auger@...hat.com>
To:     eric.auger.pro@...il.com, eric.auger@...hat.com,
        iommu@...ts.linux-foundation.org, linux-kernel@...r.kernel.org,
        kvm@...r.kernel.org, kvmarm@...ts.cs.columbia.edu, joro@...tes.org,
        will@...nel.org, robin.murphy@....com, jean-philippe@...aro.org,
        zhukeqian1@...wei.com
Cc:     alex.williamson@...hat.com, jacob.jun.pan@...ux.intel.com,
        yi.l.liu@...el.com, kevin.tian@...el.com, ashok.raj@...el.com,
        maz@...nel.org, peter.maydell@...aro.org, vivek.gautam@....com,
        shameerali.kolothum.thodi@...wei.com, wangxingang5@...wei.com,
        jiangkunkun@...wei.com, yuzenghui@...wei.com,
        nicoleotsuka@...il.com, chenxiang66@...ilicon.com,
        sumitg@...dia.com, nicolinc@...dia.com, vdumpa@...dia.com,
        zhangfei.gao@...aro.org, zhangfei.gao@...il.com,
        lushenming@...wei.com, vsethi@...dia.com
Subject: [RFC v16 9/9] iommu/smmuv3: Disallow nested mode in presence of HW MSI regions

Nested mode currently is not compatible with HW MSI reserved regions.
Indeed MSI transactions targeting those MSI doorbells bypass the SMMU.
This would require the guest to also bypass those ranges but the guest
has no information about them.

Let's check nested mode is not attempted in such configuration.

Signed-off-by: Eric Auger <eric.auger@...hat.com>
---
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 23 +++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index ddfc069c10ae..12e7d7920f27 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -2488,6 +2488,23 @@ static void arm_smmu_detach_dev(struct arm_smmu_master *master)
 	arm_smmu_install_ste_for_dev(master);
 }
 
+static bool arm_smmu_has_hw_msi_resv_region(struct device *dev)
+{
+	struct iommu_resv_region *region;
+	bool has_msi_resv_region = false;
+	LIST_HEAD(resv_regions);
+
+	iommu_get_resv_regions(dev, &resv_regions);
+	list_for_each_entry(region, &resv_regions, list) {
+		if (region->type == IOMMU_RESV_MSI) {
+			has_msi_resv_region = true;
+			break;
+		}
+	}
+	iommu_put_resv_regions(dev, &resv_regions);
+	return has_msi_resv_region;
+}
+
 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
 {
 	int ret = 0;
@@ -2545,6 +2562,12 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
 		ret = -EINVAL;
 		goto out_unlock;
 	}
+	/* Nested mode is not compatible with MSI HW reserved regions */
+	if (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED &&
+	    arm_smmu_has_hw_msi_resv_region(dev)) {
+		ret = -EINVAL;
+		goto out_unlock;
+	}
 
 	master->domain = smmu_domain;
 
-- 
2.26.3