linux-kernel - [PATCH] irqchip/gic-v3: Fix EOImode semantics in git_cpu_sys_reg

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Message-Id: <1635408092-5259-1-git-send-email-daizhiyuan@phytium.com.cn>
Date:   Thu, 28 Oct 2021 04:01:31 -0400
From:   Zhiyuan Dai <daizhiyuan@...tium.com.cn>
To:     unlisted-recipients:; (no To-header on input)
Cc:     daizhiyuan@...tium.com.cn, Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>,
        Hector Martin <marcan@...can.st>,
        Will Deacon <will@...nel.org>, linux-kernel@...r.kernel.org
Subject: [PATCH] irqchip/gic-v3: Fix EOImode semantics in git_cpu_sys_reg_init()

ICC_CTLR_EL1 is a 64-bit register.EOImode, bit [1] EOI mode
for the current Security state.

current code semantics is set ICC_CTLR_EL1 register to zero.
This patch only set the EOImode Bit to zero.

refs: See Arm IHI 0069G, page 12-229.

Signed-off-by: Zhiyuan Dai <daizhiyuan@...tium.com.cn>
---
 drivers/irqchip/irq-gic-v3.c       | 9 +++++++--
 include/linux/irqchip/arm-gic-v3.h | 3 +--
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index fd4e9a3..96466fc0 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -967,6 +967,7 @@ static void gic_cpu_sys_reg_init(void)
 	u64 need_rss = MPIDR_RS(mpidr);
 	bool group0;
 	u32 pribits;
+	u32 val;
 
 	/*
 	 * Need to check that the SRE bit has actually been set. If
@@ -1009,12 +1010,16 @@ static void gic_cpu_sys_reg_init(void)
 	 */
 	gic_write_bpr1(0);
 
+	val = gic_read_ctlr();
+
 	if (static_branch_likely(&supports_deactivate_key)) {
 		/* EOI drops priority only (mode 1) */
-		gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
+		val |= ICC_CTLR_EL1_EOImode;
+		gic_write_ctlr(val);
 	} else {
 		/* EOI deactivates interrupt too (mode 0) */
-		gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
+		val &= ~ICC_CTLR_EL1_EOImode;
+		gic_write_ctlr(val);
 	}
 
 	/* Always whack Group0 before Group1 */
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 81cbf85..1a35b24 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -544,8 +544,7 @@
  * CPU interface registers
  */
 #define ICC_CTLR_EL1_EOImode_SHIFT	(1)
-#define ICC_CTLR_EL1_EOImode_drop_dir	(0U << ICC_CTLR_EL1_EOImode_SHIFT)
-#define ICC_CTLR_EL1_EOImode_drop	(1U << ICC_CTLR_EL1_EOImode_SHIFT)
+#define ICC_CTLR_EL1_EOImode	(1U << ICC_CTLR_EL1_EOImode_SHIFT)
 #define ICC_CTLR_EL1_EOImode_MASK	(1 << ICC_CTLR_EL1_EOImode_SHIFT)
 #define ICC_CTLR_EL1_CBPR_SHIFT		0
 #define ICC_CTLR_EL1_CBPR_MASK		(1 << ICC_CTLR_EL1_CBPR_SHIFT)
-- 
1.8.3.1