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Message-ID: <20211028145447.g37g5wb632nyta3p@skbuf>
Date: Thu, 28 Oct 2021 14:54:48 +0000
From: Vladimir Oltean <vladimir.oltean@....com>
To: Clément Léger <clement.leger@...tlin.com>
CC: "David S. Miller" <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Claudiu Manoil <claudiu.manoil@....com>,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
"UNGLinuxDriver@...rochip.com" <UNGLinuxDriver@...rochip.com>,
Andrew Lunn <andrew@...n.ch>,
"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 3/3] net: ocelot: add FDMA support
On Thu, Oct 28, 2021 at 04:31:23PM +0200, Clément Léger wrote:
> > Can't we make the FDMA and the manual injection/extraction registers
> > use the same endianness, instead of duplicating code? I can
> > regression-test the manual inj/xtr regs on LS1028A.
>
> I guess this would be possible by disabling byte swapping
> (INJ_GRP_CFG.BYTE_SWAP) when sending the IFH when in register based
> mode.
> BTW, while checking performances, I noticed that the CPU spent quite a
> long time in packing so I added precomputation of IFH. I could probably
> modify the register based inj/xtr to also use this.
packing() is not the most optimized thing in the world, so I wouldn't
mind if you changed it to some other API, but the ability to read,
understand and modify the XFH/IFH headers easily is something I care
about, so no weird macros that depend upon some particular endianness,
please.
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