linux-kernel - Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded

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Message-ID: <87sfwl9oxg.wl-maz@kernel.org>
Date:   Thu, 28 Oct 2021 15:58:19 +0100
From:   Marc Zyngier <maz@...nel.org>
To:     Nikita Shubin <nikita.shubin@...uefel.me>
Cc:     guoren@...nel.org, anup@...infault.org, atish.patra@....com,
        tglx@...utronix.de, palmer@...belt.com, heiko@...ech.de,
        robh@...nel.org, linux-kernel@...r.kernel.org,
        linux-riscv@...ts.infradead.org, Guo Ren <guoren@...ux.alibaba.com>
Subject: Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded_irq with ONESHOT

On Thu, 28 Oct 2021 11:55:23 +0100,
Nikita Shubin <nikita.shubin@...uefel.me> wrote:
> 
> Hello Marc and Guo Ren!
> 
> On Mon, 25 Oct 2021 11:48:33 +0100
> Marc Zyngier <maz@...nel.org> wrote:
> 
> > On Sun, 24 Oct 2021 02:33:03 +0100,
> > guoren@...nel.org wrote:
> > > 
> > > From: Guo Ren <guoren@...ux.alibaba.com>
> > > 
> > > When using "devm_request_threaded_irq(,,,,IRQF_ONESHOT,,)" in the
> > > driver, only the first interrupt could be handled, and continue irq
> > > is blocked by hw. Because the thead,c900-plic couldn't complete
> > > masked irq source which has been disabled in enable register. Add
> > > thead_plic_chip which fix up c906-plic irq source completion
> > > problem by unmask/mask wrapper.
> > > 
> > > Here is the description of Interrupt Completion in PLIC spec [1]:
> > > 
> > > The PLIC signals it has completed executing an interrupt handler by
> > > writing the interrupt ID it received from the claim to the
> > > claim/complete register. The PLIC does not check whether the
> > > completion ID is the same as the last claim ID for that target. If
> > > the completion ID does not match an interrupt source that is
> > > currently enabled for the target, the ^^ ^^^^^^^^^ ^^^^^^^
> > > completion is silently ignored.  
> > 
> > Given this bit of the spec...
> > 
> > > +static void plic_thead_irq_eoi(struct irq_data *d)
> > > +{
> > > +	struct plic_handler *handler =
> > > this_cpu_ptr(&plic_handlers); +
> > > +	if (irqd_irq_masked(d)) {
> > > +		plic_irq_unmask(d);
> > > +		writel(d->hwirq, handler->hart_base +
> > > CONTEXT_CLAIM);
> > > +		plic_irq_mask(d);
> > > +	} else {
> > > +		writel(d->hwirq, handler->hart_base +
> > > CONTEXT_CLAIM);
> > > +	}
> > > +}
> > > +  
> > 
> > ... it isn't obvious to me why this cannot happen on an SiFive PLIC.
> 
> This indeed happens with SiFive PLIC. I am currently tinkering with
> da9063 RTC on SiFive Unmatched, and ALARM irq fires only once. However
> with changes proposed by Guo Ren in plic_thead_irq_eoi, everything
> begins to work fine.
> 
> May be these change should be propagated to plic_irq_eoi instead of
> making a new function ?

That's my impression too. I think the T-Head defect is pretty much
immaterial when you consider how 'interesting' the PLIC architecture
is. Conflating EOI and masking really is a misfeature...

	M.

-- 
Without deviation from the norm, progress is not possible.