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Message-ID: <YXtTUGC5P41JtvoR@robh.at.kernel.org>
Date: Thu, 28 Oct 2021 20:50:08 -0500
From: Rob Herring <robh@...nel.org>
To: Emil Renner Berthing <kernel@...il.dk>
Cc: linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-clk@...r.kernel.org, linux-gpio@...r.kernel.org,
linux-serial@...r.kernel.org, Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Linus Walleij <linus.walleij@...aro.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
Jiri Slaby <jirislaby@...nel.org>,
Maximilian Luz <luzmaximilian@...il.com>,
Sagar Kadam <sagar.kadam@...ive.com>,
Drew Fustini <drew@...gleboard.org>,
Geert Uytterhoeven <geert@...ux-m68k.org>,
Michael Zhu <michael.zhu@...rfivetech.com>,
Fu Wei <tekkamanninja@...il.com>,
Anup Patel <anup.patel@....com>,
Atish Patra <atish.patra@....com>,
Matteo Croce <mcroce@...rosoft.com>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 11/16] dt-bindings: pinctrl: Add StarFive JH7100
bindings
On Thu, Oct 21, 2021 at 07:42:18PM +0200, Emil Renner Berthing wrote:
> Add bindings for the StarFive JH7100 GPIO/pin controller.
>
> Signed-off-by: Emil Renner Berthing <kernel@...il.dk>
> ---
> .../pinctrl/starfive,jh7100-pinctrl.yaml | 274 ++++++++++++++++++
> 1 file changed, 274 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
> new file mode 100644
> index 000000000000..342ecd91a3b0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
> @@ -0,0 +1,274 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7100 Pin Controller Device Tree Bindings
> +
> +maintainers:
> + - Emil Renner Berthing <kernel@...il.dk>
> + - Drew Fustini <drew@...gleboard.org>
> +
> +properties:
> + compatible:
> + const: starfive,jh7100-pinctrl
> +
> + reg:
> + minItems: 2
> + maxItems: 2
> +
> + reg-names:
> + items:
> + - const: "gpio"
> + - const: "padctl"
Don't need quotes.
> +
> + clocks:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + gpio-controller: true
> +
> + "#gpio-cells":
> + const: 2
> + description: |
> + Number of cells in GPIO specifier. Since the generic GPIO
> + binding is used, the amount of cells must be specified as 2.
> +
> + interrupts:
> + maxItems: 1
> + description: The GPIO parent interrupt.
> +
> + interrupt-controller: true
> +
> + "#interrupt-cells":
> + const: 2
> +
> + starfive,signal-group:
> + description: |
> + The SoC has a global setting selecting one of 7 different pinmux
> + configurations of the pads named GPIO[0:63] and FUNC_SHARE[0:141]. After
> + this global setting is chosen only the 64 "GPIO" pins can be further
> + muxed by configuring them to be controlled by certain peripherals rather
> + than software.
> + Note that in configuration 0 none of GPIOs are routed to pads, and only
> + in configuration 1 are the GPIOs routed to the pads named GPIO[0:63].
> + If this property is not set it defaults to the configuration already
> + chosen by the earlier boot stages.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2, 3, 4, 5, 6]
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - gpio-controller
> + - "#gpio-cells"
> + - interrupts
> + - interrupt-controller
> + - "#interrupt-cells"
> +
> +patternProperties:
> + '-[0-9]*$':
Can you make this more specific. As-is, '-' and 'foo-' are valid.
> + type: object
> + patternProperties:
> + '-pins*$':
So foo-pinsssssss is okay? Drop the '*' or use ? if you intend to
support 'foo-pin'.
> + type: object
> + description: |
> + A pinctrl node should contain at least one subnode representing the
> + pinctrl groups available on the machine. Each subnode will list the
> + pins it needs, and how they should be configured, with regard to
> + muxer configuration, bias, input enable/disable, input schmitt
> + trigger enable/disable, slew-rate and drive strength.
> + $ref: "/schemas/pinctrl/pincfg-node.yaml"
> +
> + properties:
> + pins:
> + description: |
> + The list of pin identifiers that properties in the node apply to.
> + This should be set using either the PAD_GPIO or PAD_FUNC_SHARE
> + macro. Either this or "pinmux" has to be specified.
> +
> + pinmux:
> + description: |
> + The list of GPIO identifiers and their mux settings that
> + properties in the node apply to. This should be set using the
> + GPIOMUX macro. Either this or "pins" has to be specified.
> +
> + bias-disable: true
> +
> + bias-pull-up:
> + type: boolean
Already has a type. Need to reference the common schema.
> +
> + bias-pull-down:
> + type: boolean
> +
> + drive-strength:
> + enum: [ 14, 21, 28, 35, 42, 49, 56, 63 ]
> +
> + input-enable: true
> +
> + input-disable: true
> +
> + input-schmitt-enable: true
> +
> + input-schmitt-disable: true
> +
> + slew-rate:
> + maximum: 7
> +
> + starfive,strong-pull-up:
> + description: enable strong pull-up.
> + type: boolean
> +
> + additionalProperties: false
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/starfive-jh7100.h>
> + #include <dt-bindings/reset/starfive-jh7100.h>
> + #include <dt-bindings/pinctrl/pinctrl-starfive.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + gpio: pinctrl@...10000 {
> + compatible = "starfive,jh7100-pinctrl";
> + reg = <0x0 0x11910000 0x0 0x10000>,
> + <0x0 0x11858000 0x0 0x1000>;
> + reg-names = "gpio", "padctl";
> + clocks = <&clkgen JH7100_CLK_GPIO_APB>;
> + resets = <&clkgen JH7100_RSTN_GPIO_APB>;
> + interrupts = <32>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + starfive,signal-group = <6>;
> +
> + gmac_pins_default: gmac-0 {
> + gtxclk-pins {
> + pins = <PAD_FUNC_SHARE(115)>;
> + bias-pull-up;
> + drive-strength = <35>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + };
> + miitxclk-pins {
> + pins = <PAD_FUNC_SHARE(116)>;
> + bias-pull-up;
> + drive-strength = <14>;
> + input-enable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + tx-pins {
> + pins = <PAD_FUNC_SHARE(117)>,
> + <PAD_FUNC_SHARE(119)>,
> + <PAD_FUNC_SHARE(120)>,
> + <PAD_FUNC_SHARE(121)>,
> + <PAD_FUNC_SHARE(122)>,
> + <PAD_FUNC_SHARE(123)>,
> + <PAD_FUNC_SHARE(124)>,
> + <PAD_FUNC_SHARE(125)>,
> + <PAD_FUNC_SHARE(126)>;
> + bias-disable;
> + drive-strength = <35>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + rxclk-pins {
> + pins = <PAD_FUNC_SHARE(127)>;
> + bias-pull-up;
> + drive-strength = <14>;
> + input-enable;
> + input-schmitt-disable;
> + slew-rate = <6>;
> + };
> + rxer-pins {
> + pins = <PAD_FUNC_SHARE(129)>;
> + bias-pull-up;
> + drive-strength = <14>;
> + input-enable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + rx-pins {
> + pins = <PAD_FUNC_SHARE(128)>,
> + <PAD_FUNC_SHARE(130)>,
> + <PAD_FUNC_SHARE(131)>,
> + <PAD_FUNC_SHARE(132)>,
> + <PAD_FUNC_SHARE(133)>,
> + <PAD_FUNC_SHARE(134)>,
> + <PAD_FUNC_SHARE(135)>,
> + <PAD_FUNC_SHARE(136)>,
> + <PAD_FUNC_SHARE(137)>,
> + <PAD_FUNC_SHARE(138)>,
> + <PAD_FUNC_SHARE(139)>,
> + <PAD_FUNC_SHARE(140)>,
> + <PAD_FUNC_SHARE(141)>;
> + bias-pull-up;
> + drive-strength = <14>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + };
> + };
> +
> + i2c0_pins_default: i2c0-0 {
> + i2c-pins {
> + pinmux = <GPIOMUX(62, GPO_LOW,
> + GPO_I2C0_PAD_SCK_OEN,
> + GPI_I2C0_PAD_SCK_IN)>,
> + <GPIOMUX(61, GPO_LOW,
> + GPO_I2C0_PAD_SDA_OEN,
> + GPI_I2C0_PAD_SDA_IN)>;
> + bias-disable; /* external pull-up */
> + input-enable;
> + input-schmitt-enable;
> + };
> + };
> +
> + uart3_pins_default: uart3-0 {
> + rx-pin {
> + pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
> + GPI_UART3_PAD_SIN)>;
> + bias-pull-up;
> + input-enable;
> + input-schmitt-enable;
> + };
> + tx-pin {
> + pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
> + GPO_ENABLE, GPI_NONE)>;
> + bias-disable;
> + input-disable;
> + input-schmitt-disable;
> + };
> + };
> + };
> +
> + gmac {
> + pinctrl-0 = <&gmac_pins_default>;
> + pinctrl-names = "default";
> + };
> +
> + i2c0 {
> + pinctrl-0 = <&i2c0_pins_default>;
> + pinctrl-names = "default";
> + };
> +
> + uart3 {
> + pinctrl-0 = <&uart3_pins_default>;
> + pinctrl-names = "default";
> + };
> + };
> +
> +...
> --
> 2.33.1
>
>
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