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Date: Fri, 29 Oct 2021 17:02:05 -0700 From: <quic_vamslank@...cinc.com> To: <agross@...nel.org>, <bjorn.andersson@...aro.org>, <olof@...om.net>, <soc@...nel.org>, <linus.walleij@...aro.org>, <sboyd@...eaurora.org>, <robh+dt@...nel.org> CC: <linux-arm-msm@...r.kernel.org>, <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>, <linux-gpio@...r.kernel.org>, <manivannan.sadhasivam@...aro.org>, Vamsi krishna Lanka <quic_vamslank@...cinc.com> Subject: [PATCH v3 3/3] ARM: dts: qcom: sdx65: Add pincontrol node From: Vamsi krishna Lanka <quic_vamslank@...cinc.com> This commit adds pincontrol node to SDX65 dts. Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@...cinc.com> --- arch/arm/boot/dts/qcom-sdx65.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 5aecb00..796641d 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -91,6 +91,18 @@ status = "disabled"; }; + tlmm: pinctrl@...0000 { + compatible = "qcom,sdx65-tlmm"; + reg = <0xf100000 0x300000>; + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 109>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; + pdc: interrupt-controller@...0000 { compatible = "qcom,sdx65-pdc", "qcom,pdc"; reg = <0xb210000 0x10000>; -- 2.7.4
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